Techniques for Design and Implementation of an FPGA-Specific Physical Unclonable Function
Techniques for Design and Implementation of an FPGA-Specific Physical Unclonable Function
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DOI：
10.1007/s11390-016-1616-8
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发表时间：
2016-01
影响因子：
0.7
通讯作者：
Jiliang Zhang;Qiang Wu;Yipeng Ding;Yong-Qiang Lv;Qiang Zhou;Zhihua Xia;Xingming Sun;Xingwei Wang
中科院分区：
文献类型：
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作者：
Jiliang Zhang;Qiang Wu;Yipeng Ding;Yong-Qiang Lv;Qiang Zhou;Zhihua Xia;Xingming Sun;Xingwei Wang
物理不可克隆功能（PUF）利用IC生产过程中不可控的工艺变化为每个IC生成唯一的签名。它在FPGA知识产权保护、密钥生成、数字版权管理等安全领域有着广泛的应用。环形振荡器（RO）PUF和仲裁器PUF是最流行的PUF，但它们不是专门为FPGA设计的。RO PUF在获得较少的挑战-响应对的同时引起高资源开销，并且需要“硬宏”来在FPGA上实现。仲裁器PUF的资源开销小，但其结构在FPGA上映射时存在较大偏差。安德森PUF可以解决目前在FPGA上实现的仲裁器和RO PUF的这些弱点。但是，它不能直接在新一代28 nm FPGA上实现。为了解决这些问题，本文设计并实现了一种基于延迟的PUF，该PUF在SLICEM中使用两个LUT来实现PUF的两个16位移位寄存器，在进位链中使用2到1复用器来实现PUF的复用器，并且使用8个触发器中的任何一个来锁存1位PUF签名。在28 nm商用FPGA上完全实现了所提出的基于延迟的PUF，实验结果表明其具有很高的唯一性、可靠性和可重构性。此外，我们测试了老化对其的影响，结果表明，老化对所提出的PUF的影响是微不足道的，只有6%的位翻转。最后，讨论了PUF在FPGA绑定和易失性密钥生成中的应用前景。
Physical unclonable function (PUF) makes use of the uncontrollable process variations during the production of IC to generate a unique signature for each IC. It has a wide application in security such as FPGA intellectual property (IP) protection, key generation and digital rights management. Ring oscillator (RO) PUF and Arbiter PUF are the most popular PUFs, but they are not specially designed for FPGA. RO PUF incurs high resource overhead while obtaining less challenge-response pairs, and requires "hard macros" to implement on FPGAs. The arbiter PUF brings low resource overhead, but its structure has big bias when it is mapped on FPGAs. Anderson PUF can address these weaknesses of current Arbiter and RO PUFs implemented on FPGAs. However, it cannot be directly implemented on the new generation 28 nm FPGAs. In order to address these problems, this paper designs and implements a delay-based PUF that uses two LUTs in an SLICEM to implement two 16-bit shift registers of the PUF, 2-to-1 multiplexers in the carry chain to implement the multiplexers of the PUF, and any one of the 8 flip-flops to latch 1-bit PUF signatures. The proposed delay-based PUF is completely realized on 28 nm commercial FPGAs, and the experimental results show its high uniqueness, reliability and reconfigurability. Moreover, we test the impact of aging on it, and the results show that the effect of aging on the proposed PUF is insignificant, with only 6% bit-flips. Finally, the prospects of the proposed PUF in the FPGA binding and volatile key generation are discussed.