340 mV-1.1 V, 289 Gbps/W, 2090-Gate NanoAES Hardware Accelerator With Area-Optimized Encrypt/Decrypt GF(24)2 Polynomials in 22 nm Tri-Gate CMOS
340 mV-1.1 V, 289 Gbps/W, 2090-Gate NanoAES Hardware Accelerator With Area-Optimized Encrypt/Decrypt GF(24)2 Polynomials in 22 nm Tri-Gate CMOS
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DOI：
10.1109/jssc.2014.2384039
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发表时间：
2015-04-01
影响因子：
5.4
通讯作者：
Krishnamurthy, Ram
中科院分区：
文献类型：
--
作者：
Mathew, Sanu;Satpathy, Sudhir;Krishnamurthy, Ram
本文介绍了一种片上轻量级 nanoAES 硬件加速器，采用 22 nm 三栅高 k/金属栅 CMOS 制造，专门用于移动 SOC 上的超低功耗对称密钥加密和解密。与传统的 128 位 AES 实现相比，此设计使用单个 8 位 Sbox 电路以及 ShiftRows 字节顺序数据处理来计算本机 GF(2(4))(2) 复合字段中的所有 AES 轮次。这种方法与串行累加 MixColumns 电路、面积优化的加密和解密伽罗瓦域多项式以及集成的动态密钥生成电路相结合，形成了紧凑的加密/解密布局，分别占用 2200/2736 μ m(2) 和报告的最低门数 1947/2090，同时实现：(i) 最大工作频率为 1.133 GHz，总功耗为 13 mW，泄漏分量为 500 mu W，在 0.9 V、25 摄氏度下测量，(ii) 标称 AES-128 加密/解密吞吐量分别为 432/671 Mbps，在 430 mV 的近阈值操作下测量的峰值能效为 289 Gbps/W（比之前报告的实现高 11 倍），(iii) 加密/解密延迟分别为 336/216 个周期和 3.9/2.5 nJ 的总能耗，(iv) 宽工作电源电压范围，在 340 mV、25 摄氏度下测量，具有 45 Mbps、170 muW 的稳健亚阈值电压性能，以及 (v) 首次报告的基于伽罗瓦域多项式的微架构协同优化，产生独特的区域优化加密和解密多项式在同等性能下，面积减少高达 9%。
This paper describes an on-die lightweight nanoAES hardware accelerator, fabricated in 22 nm tri-gate high-k/metal-gate CMOS, targeted for ultra-low power symmetric-key encryption and decryption on mobile SOCs. Compared to conventional 128 bit AES implementations, this design uses a single 8 bit Sbox circuit along with ShiftRows byte-order data processing to compute all AES rounds in native GF(2(4))(2) composite-field. This approach along with a serial-accumulating MixColumns circuit, area-optimized encrypt and decrypt Galois-field polynomials and integrated on-the-fly key generation circuit results in a compact encrypt/decrypt layout occupying 2200/2736 mu m(2) and lowest-reported gate count of 1947/2090 respectively, while achieving: (i) maximum operating frequency of 1.133 GHz and total power consumption of 13 mW with leakage component of 500 mu W, measured at 0.9 V, 25 degrees C, (ii) nominal AES-128 encrypt/decrypt throughput of 432/671 Mbps respectively, with peak energy-efficiency of 289 Gbps/W measured at near-threshold operation of 430 mV (11 x higher than previously reported implementations), (iii) encrypt/decrypt latencies of 336/216 cycles and total energy consumption of 3.9/2.5 nJ respectively, (iv) wide operating supply voltage range with robust sub-threshold voltage performance of 45 Mbps, 170 mu W, measured at 340 mV, 25 degrees C and (v) first-reported Galois-field polynomial-based micro-architectural co-optimization, resulting in distinct area-optimized encrypt and decrypt polynomials with up to 9% area reduction at iso-performance.