Techniques for the creation of digital watermarks in sequentialcircuit designs
Techniques for the creation of digital watermarks in sequentialcircuit designs
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DOI：
10.1109/43.945306
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发表时间：
2001-09
期刊：
影响因子：
--
通讯作者：
Arlindo L. Oliveira
中科院分区：
文献类型：
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作者：
Arlindo L. Oliveira
我们提出了一种同步时序电路的水印的方法，使它能够通过施加数字水印的状态转换图（STG）的电路，以确定作者的设计。该方法适用于顺序设计，可作为公司的知识产权，通常用于表征设计指定为结构硬件描述语言或电路网表的指定。水印是通过操纵的STG的设计，以这样的方式，使它表现出一个选定的属性，这是非常罕见的非水印电路，而在同一时间，不改变电路的功能。这种操作是在没有以隐式或显式形式实际计算该图的情况下执行的。相反，数字水印是通过直接操纵电路描述来获得的。我们提出的证据表明，没有已知的算法电路操作可以用来有效地删除或改变水印，该过程是免疫各种其他攻击。我们提出的理论和实验结果表明，水印可以有效地创建和验证。我们还测试了可能的攻击策略，并验证它们不适用于中等到大复杂度的现实设计。
We present a methodology for the watermarking of synchronous sequential circuits that makes it possible to identify the authorship of designs by imposing a digital watermark on the state transition graph (STG) of the circuit. The methodology is applicable to sequential designs that are made available as firm intellectual property, the designation commonly used to characterize designs specified as structural hardware description languages or circuit netlists. The watermarking is obtained by manipulating the STG of the design in such a way as to make it exhibit a chosen property that is extremely rare in nonwatermarked circuits while, at the same time, not changing the functionality of the circuit. This manipulation is performed without ever actually computing this graph in either implicit or explicit form. Instead, the digital watermark is obtained by direct manipulation of the circuit description. We present evidence that no known algorithms for circuit manipulation can be used to efficiently remove or change the watermark and that the process is immune to a variety of other attacks. We present both theoretical and experimental results that show that the watermarking can be created and verified efficiently. We also test possible attack strategies and verify that they are inapplicable to realistic designs of medium to large complexity.