Small footprint transistor architecture for photoswitching logic and in situ memory
Small footprint transistor architecture for photoswitching logic and in situ memory
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用于光开关逻辑和原位存储器的小尺寸晶体管架构
DOI：
10.1038/s41565-019-0462-6
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发表时间：
2019-07-01
影响因子：
38.3
通讯作者：
Zhou, Peng
中科院分区：
文献类型：
--
作者：
Liu, Chunsen;Chen, Huawei;Zhou, Peng
对硅晶体管尺寸不断缩小的需求正在推动工业发展战略，以进一步减少占地面积（1，2）。二维材料的原子厚度允许高面积效率晶体管架构的潜在实现。然而，到目前为止，由二维材料组成的器件的设计已经模仿了硅电路的基本架构（3-6）。在这里，我们报告了一种基于二维材料的晶体管，它可以在单个单元中实现光开关逻辑（OR，AND）计算。与传统的晶体管工作机制不同，二维材料逻辑晶体管具有两个表面沟道。此外，材料厚度可以改变逻辑行为-架构可以灵活扩展，以实现在同一设备中的逻辑计算和数据存储收敛等原位存储。这些器件是构建新芯片的潜在候选者，这些芯片可以以高面积效率和独特功能执行计算和存储。
The need for continuous size downscaling of silicon transistors is driving the industrial development of strategies to enable further footprint reduction(1,2). The atomic thickness of two-dimensional materials allows the potential realization of high-area-efficiency transistor architectures. However, until now, the design of devices composed of two-dimensional materials has mimicked the basic architecture of silicon circuits(3-6). Here, we report a transistor based on a two-dimensional material that can realize photoswitching logic (OR, AND) computing in a single cell. Unlike the conventional transistor working mechanism, the two-dimensional material logic transistor has two surface channels. Furthermore, the material thickness can change the logic behaviour-the architecture can be flexibly expanded to achieve in situ memory such as logic computing and data storage convergence in the same device. These devices are potentially promising candidates for the construction of new chips that can perform computing and storage with high area-efficiency and unique functions.