A SW performance estimation framework for early system-level-design using fine-grained instrumentation
A SW performance estimation framework for early system-level-design using fine-grained instrumentation
复制标题
使用细粒度仪器进行早期系统级设计的软件性能估计框架
DOI：
10.1109/date.2006.243830
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发表时间：
2006
期刊：
影响因子：
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通讯作者：
H. Meyr
中科院分区：
文献类型：
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作者：
T. Kempf;K. Karuri;Stefan Wallentowitz;G. Ascheid;R. Leupers;H. Meyr
随着嵌入式应用对高性能的需求日益增长，系统架构师们越来越倾向于采用多个可编程器件的多处理器片上系统（MP-SoC）。可编程内核提供了高度的灵活性和可重用性，并且可以根据应用程序的要求进行优化，以提供高性能。由于应用软件构成了此类设计的基础，因此调整底层SoC架构以从软件代码中提取最大性能的需求已变得势在必行。在本文中，我们提出了一个框架，使软件开发，验证和评估从一开始的MP-SoC设计周期。与传统的SoC设计流程不同，软件设计仅在初始SoC架构准备就绪后才开始，我们的框架允许在紧密耦合的循环中共同开发硬件和软件组件，其中硬件可以通过逐步考虑软件的要求来改进。该框架的关键要素是将细粒度软件插装工具集成到系统级设计（SLD）环境中，以获得准确的软件性能和内存访问统计数据。这种统计的准确性是通过指令集仿真（ISS）获得的，而仪表软件的执行速度几乎是一个数量级快于ISS。这样的组合设计方法有助于系统架构师通过快速的探索周期来优化硬件和软件，并且可以大大缩短设计周期和提高生产率。我们从两个最突出的和计算密集型的嵌入式应用领域中选择了两个案例研究，证明了我们的方法的通用性和效率
The increasing demands of high-performance in embedded applications under shortening time-to-market has prompted system architects in recent time to opt for multi-processor systems-on-chip (MP-SoCs) employing several programmable devices. The programmable cores provide a high amount of flexibility and reusability, and can be optimized to the requirements of the application to deliver high-performance as well. Since application software forms the basis of such designs, the need to tune the underlying SoC architecture for extracting maximum performance from the software code has become imperative. In this paper, we propose a framework that enables software development, verification and evaluation from the very beginning of MP-SoC design cycle. Unlike traditional SoC design flows where software design starts only after the initial SoC architecture is ready, our framework allows a co-development of the hardware and the software components in a tightly coupled loop where the hardware can be refined by considering the requirements of the software in a stepwise manner. The key element of this framework is the integration of a fine-grained software instrumentation tool into a system-level-design (SLD) environment to obtain accurate software performance and memory access statistics. The accuracy of such statistics is comparable to that obtained through instruction set simulation (ISS), while the execution speed of the instrumented software is almost an order of magnitude faster than ISS. Such a combined design approach assists system architects to optimize both the hardware and the software through fast exploration cycles, and can result in far shorter design cycles and high productivity. We demonstrate the generality and the efficiency of our methodology with two case studies selected from two most prominent and computationally intensive embedded application domains