A 0.79 pJ/K-Gate, 83% Efficient Unified Core and Voltage Regulator Architecture for Sub/Near-Threshold Operation in 130 nm CMOS
A 0.79 pJ/K-Gate, 83% Efficient Unified Core and Voltage Regulator Architecture for Sub/Near-Threshold Operation in 130 nm CMOS
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A%200.79%20pJ/K-Gate、%2083%%20Efficient%20Unified%20Core%20and%20Voltage%20Regulator%20Architecture%20for%20Sub/Near-Threshold%20Operation%20in%20130%20nm%20CMOS
DOI：
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发表时间：
2014
影响因子：
5.4
通讯作者：
P. Krein
中科院分区：
文献类型：
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作者：
Sai Zhang;J. Tu;Naresh R Shanbhag;P. Krein
本文介绍了计算电压调节器模块（C-VRM），一种架构，嵌入到超低功耗（ULP）平台的能量输送子系统的信息处理子系统。C-VRM采用多电压域堆叠和核心交换，以实现近/亚阈值区域的高总系统能量效率。能量模型的C-VRM的推导，并在系统仿真中比较的C-VRM的开关电容VRM（SC-VRM）的能源效率的好处。采用1.2 V、130 nm CMOS工艺实现了一个集成C-VRM和SC-VRM的8抽头全折叠FIR滤波器芯片原型。测量结果表明，与SC-VRM系统相比，C-VRM系统的系统级每操作能量（Eop）节省高达44.8%，并且在0.52 V至0.6 V的输出电压范围内，效率η范围为79%至83%。Eop和η的测量值与系统仿真预测的值相匹配，从而验证了能量模型。
This paper presents the compute voltage regulator module (C-VRM), an architecture that embeds the information processing subsystem into the energy delivery subsystem for ultra-low power (ULP) platforms. The C-VRM employs multiple voltage domain stacking and core swapping to achieve high total system energy efficiency in near/sub-threshold region. Energy models for the C-VRM are derived, and employed in system simulations to compare the energy efficiency benefits of the C-VRM over a switched capacitor VRM (SC-VRM). A prototype IC incorporating a C-VRM and a SC-VRM supplying energy to an 8-tap fully folded FIR filter core is implemented in a 1.2 V, 130 nm CMOS process. Measured results indicate that the C-VRM has up to 44.8% savings in system-level energy per operation (Eop) compared to the SC-VRM system, and an efficiency η ranging from 79% to 83% over an output voltage range of 0.52 V to 0.6 V. Measured values of the Eop and η match those predicted by system simulations thereby validating the energy models.