SRAM Write-Ability Improvement With Transient Negative Bit-Line Voltage
SRAM Write-Ability Improvement With Transient Negative Bit-Line Voltage
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DOI：
10.1109/tvlsi.2009.2029114
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发表时间：
2011
影响因子：
2.8
通讯作者：
S. Mukhopadhyay;R. Rao;Jae-Joon Kim;C. Chuang
中科院分区：
文献类型：
--
作者：
S. Mukhopadhyay;R. Rao;Jae-Joon Kim;C. Chuang
器件参数变化的增加会显着降低深亚 100 nm CMOS 技术中 SRAM 单元的写入能力。本文提出了一种瞬态负位线电压技术来提高 SRAM 单元的写入能力。电容耦合用于在写操作期间在低位位线上生成瞬态负电压，而不使用任何片上或片外负电压源。 45 nm PD/SOI 技术的统计模拟表明，采用所提出的方法，写入失败概率降低了 103 倍。
Increasing variations in device parameters significantly degrades the write-ability of SRAM cells in deep sub-100 nm CMOS technology. In this paper, a transient negative bit-line voltage technique is presented to improve write-ability of SRAM cell. Capacitive coupling is used to generate a transient negative voltage at the low-going bit-line during Write operation without using any on-chip or off-chip negative voltage source. Statistical simulations in a 45-nm PD/SOI technology show a 103X reduction in the Write-failure probability with the proposed method.