Experimental Analysis of Substrate Noise Effect on PLL Performance
Experimental Analysis of Substrate Noise Effect on PLL Performance
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基板噪声对 PLL 性能影响的实验分析
DOI：
10.1109/tcsii.2008.921582
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发表时间：
2008
期刊：
影响因子：
--
通讯作者：
H. Ainspan
中科院分区：
文献类型：
--
作者：
W. Rhee;K. Jenkins;J. Liobe;H. Ainspan
介绍了一种分析衬底噪声对锁相环性能影响的实验方法。考虑锁相环的噪声传递函数的频谱分析用于识别锁相环的衬底噪声敏感元件。通过分析频谱分析仪中看到的边带，确认了了解PLL环路动态和噪声传递函数的重要性。研究还得出结论：与压控振荡器不同，PLL模块对衬底噪声耦合更敏感，这取决于衬底噪声频率。此外，结果表明，参考时钟频率附近的互调可能是分数N锁相环产生边带的主要来源。
This paper describes experimental approaches to analyze the effect of the substrate noise on phase-locked loop (PLL) performance. Spectral analysis considering noise transfer functions of the PLL is used to identify the substrate-noise sensitive components of the PLL. Analyzing the sidebands seen in a spectrum analyzer confirms the importance of knowing the PLL loop dynamics and noise transfer functions. It also leads to the conclusion that the PLL blocks other than the VCO can be more sensitive to substrate noise coupling, depending on the substrate noise frequency. Furthermore, the result shows that intermodulation near the reference clock frequency could be a dominant source of generating sidebands in fractional-N PLLs.