DyRACT: A partial reconfiguration enabled accelerator and test platform
DyRACT: A partial reconfiguration enabled accelerator and test platform
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DyRACT：支持部分重新配置的加速器和测试平台
DOI：
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发表时间：
2014
期刊：
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通讯作者：
Suhaib A. Fahmy
中科院分区：
文献类型：
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作者：
Kizheppatt Vipin;Suhaib A. Fahmy
将FPGA与通用计算机集成仍然很困难，但最近的努力已经产生了开放式框架，该框架提供了软件API和硬件接口，以允许更容易的集成。然而，这样的系统仅支持静态FPGA设计。通过添加部分重新配置（PR）支持，此类框架可以更有效地使用FPGA。现在，设计人员可以将硬件加速器集成到他们的软件应用程序中，并且可以根据需要动态加载。我们提出了一个PR启用FPGA平台，允许用户模块加载到FPGA上，输入应用，获得的结果，并在运行时交换功能。接口和PR管理逻辑是静态区域的一部分，而多个加速器可以使用由API提供的高级功能来加载。通过PCIe接口从主机PC管理重新配置和数据传输，通信吞吐量超过1.5 GB/s（峰值PCIe带宽的75%），在20 ms内重新配置大型加速器。
Integrating FPGAs with a general purpose computer remains difficult, but recent efforts have resulted in open frameworks that offer a software API and hardware interface to allow easier integration. However, such systems only support static FPGA designs. With the addition of partial reconfiguration (PR) support, such frameworks can enable more effective use of FPGAs. Now, designers can incorporate hardware accelerators within their software applications, and these can be loaded dynamically as required. We present a PR-enabled FPGA platform that allows user modules to be loaded onto the FPGA, inputs to be applied, results obtained, and functions to be swapped at runtime. The interface and PR management logic are part of the static region, while multiple accelerators can be loaded using high level functions provided by the API. Reconfiguration and data transfer are both managed over the PCIe interface from the host PC, with communication throughput of more than 1.5 GB/s (75% of peak PCIe bandwidth) and reconfiguration of a large accelerator in 20 ms.