Low-Distortion Wideband Delta-Sigma ADCs With Shifted Loop Delays
Low-Distortion Wideband Delta-Sigma ADCs With Shifted Loop Delays
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DOI：
10.1109/tcsi.2014.2362972
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发表时间：
2015-02
期刊：
影响因子：
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通讯作者：
Xin Meng;Yi Zhang;Tao He;G. Temes
中科院分区：
文献类型：
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作者：
Xin Meng;Yi Zhang;Tao He;G. Temes
提出了几种新型的低功耗、低失真的移位环路延迟Δ ∑调制器拓扑结构。单采样和双采样调制器进行了讨论。所提出的架构可以放宽量化和动态元素匹配的关键时序。最后一级的无延迟积分器用于执行有源求和，从而消除了有源加法器。最后一个积分器的输入摆幅减小，放松了OTA的要求。该拓扑简化了前馈路径，节省了功耗和电容面积。噪声耦合技术也可以用来增强噪声整形。为了验证该拓扑结构的效果，分别对单采样和双采样三阶Δ PWM调制器在有噪声耦合和无噪声耦合情况下的性能进行了分析和仿真。
This paper presents several novel low-power low-distortion ΔΣ modulator topologies with shifted loop delays. Both single-sampled and double-sampled modulators are discussed. The proposed architectures can relax the critical timing for quantization and for dynamic element matching. A delay-free integrator in the last stage is used to perform the active summation, hence eliminating the active adder. The reduced input swing of the last integrator relaxes the OTA's requirements. The proposed topology simplifies the feed-forward paths, and saves power consumption and capacitor area. Noise-coupled technique can also be utilized to enhance the noise shaping. To verify the effect of the proposed topology, single- and double-sampled third-order ΔΣ modulators with and without noise coupling were analyzed and simulated.