Thermal performance of CMOS-SOI transistors from weak to strong inversion
Thermal performance of CMOS-SOI transistors from weak to strong inversion
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DOI：
10.1109/mim.2012.6314512
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发表时间：
2012-10
影响因子：
2.1
通讯作者：
M. Malits;D. Corcos;A. Svetlitza;D. Elad;Y. Nemirovsky
中科院分区：
文献类型：
--
作者：
M. Malits;D. Corcos;A. Svetlitza;D. Elad;Y. Nemirovsky
互补金属氧化物半导体（CMOS）在22纳米及以后的技术节点上继续发展的一个有前途的解决方案是CMOS-绝缘体上硅（SOI），它特别用于低功耗和“片上系统”应用。CMOS-SOI涉及在非常薄的晶体硅层上构建传统的mosfet。用一层厚的埋置SiO2薄膜将硅薄层与衬底隔开，从而使器件与衬底以及器件之间相互隔离。CMOS-SOI技术已经成为广泛应用的领先技术，其中集成的CMOS-SOI微机电系统或纳米机电系统（MEMS/NEMS）技术为红外和太赫兹（THz）成像仪提供独特的传感系统。CMOS-SOI技术传统上分为部分耗尽（当硅器件层比最大栅极耗尽宽度厚时）和完全耗尽器件（当器件层在达到阈值电压之前完全耗尽时）。它也可以像所有CMOS技术一样，根据最小通道长度Lmin进行分类。本研究的重点是部分耗尽的0.18 RF CMOS-SOI技术[4]，重点是弱反转区和强反转区。由于该工艺成熟且成本相对较低，因此适用于混合信号设计，而本文提出的方法和结果可以扩展到任何先进的CMOS-SOI纳米晶体管。本研究的结果可以提供一个系统的方法来评估CMOS-SOI晶体管在广泛温度范围内工作的热行为。
A promising solution to continue the complementary metal-oxide semiconductor (CMOS) scaling roadmap at the 22 nm technology node and beyond is CMOS-silicon on insulator (SOI), which is used especially in low-power and "system on chip" applications. CMOS-SOI involves building conventional MOSFETs on very thin layers of crystalline silicon. The thin layer of silicon is separated from the substrate by a thick layer of buried SiO2 film, thus isolating the devices from the underlying silicon substrate and from each other. CMOS-SOI technology is already a leading technology in a wide range of applications where integrated CMOS-SOI-microelectromechanical systems or nanoelectromechanical systems (MEMS/NEMS) technologies provide unique sensing systems for IR and terahertz (THz) imagers. CMOS-SOI technology is traditionally classified into partially depleted (when the silicon device layer is thicker than the maximum gate depletion width) and fully depleted devices (when the device layer is fully depleted before the threshold voltage is reached). It may also be classified, like all CMOS technology, according to the minimal channel length, Lmin. This study focuses on partially depleted 0.18 RF CMOS-SOI technologies [4] with emphasis on the weak and strong inversion regions. This process is suitable for mixed-signal design because of its maturity and relatively low cost, while the methodology and results presented here may be extended to any advanced CMOS-SOI nano-transistors. The results of this study may provide a systematic approach to assessing the thermal behavior of CMOS-SOI transistors operating in a wide range of temperatures.