Toward Hardware-Based IP Vulnerability Detection and Post-Deployment Patching in Systems-on-Chip
Toward Hardware-Based IP Vulnerability Detection and Post-Deployment Patching in Systems-on-Chip
复制标题
片上系统中基于硬件的 IP 漏洞检测和部署后修补
DOI：
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发表时间：
2021
影响因子：
2.9
通讯作者：
K. Chakrabarty
中科院分区：
文献类型：
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作者：
Benjamin Tan;Rana Elnaggar;Jason M. Fung;R. Karri;K. Chakrabarty
系统集成商通过集成众多第三方知识产权模块（3pip）来实现特定于应用程序的设计目标，从而创建异构片上系统（soc）。随着知识产权（IP）复杂性的增加，3pip可能会受到硬件错误的影响，或者可能无意中向SoC引入其他软件可利用的安全威胁。为了确保新SoC的持续生存能力，我们需要在SoC部署后修补新发现的IP问题的基础设施。为了应对3pip带来的日益增加的风险，我们探讨了在硬件中实现监控和缓解功能的可行性和局限性。我们提出的监控和缓解补丁（MoP）块提供了针对以ip为中心的关键问题的防御基础，重点关注系统集成商仅具有3PIP设计的接口级可见性的情况。MoPs分布在整个SoC中，直接监控和缓解硬件问题，并透明地监控潜在的受损软件——MoPs对运行时受损的软件和固件具有弹性。我们通过使用嵌入式fpga或作为可重新编程的固定设计模块来实现这些监视器，确保它们在部署后可重新配置。我们对许多ip类型进行了案例研究，并对ip中与安全相关的问题和错误进行了建模，探讨了相对复杂性和潜在的资源开销。我们的研究表明了我们提出的方法的实用性，在Cyclone V FPGA中，MoP模块需要不到1.5%的自适应逻辑模块（alm）来进行接口监控和每个IP的问题缓解。
System integrators create heterogeneous systems-on-chip (SoCs) by integrating numerous third-party intellectual property blocks (3PIPs) to achieve application-specific design goals. With increasing intellectual property (IP) complexity, 3PIPs can suffer from hardware bugs or they can inadvertently introduce other software-exploitable security threats to the SoC. To ensure the ongoing survivability of new SoCs, we need infrastructure for patching newly discovered IP issues after an SoC has been deployed. To address the increasing risks from 3PIPs, we explore the feasibility and limitations of implementing monitoring and mitigation capabilities in hardware. Our proposed monitoring and mitigation patch (MoP) blocks provide a defensive foundation against critical IP-centric issues, focusing on situations where a system integrator only has interface-level visibility of 3PIP designs. The MoPs are distributed throughout the SoC to monitor and mitigate issues directly in hardware and transparently for potentially compromised software—the MoPs are resilient against run-time compromised software and firmware. We ensure that these monitors are reconfigurable after deployment by implementing them using embedded-FPGAs or as a reprogrammable, fixed-design module. We perform a case study of numerous IP-types and model a selection of security-relevant issues and bugs in the IPs, exploring the relative complexity and potential resource overhead. Our study shows the utility of our proposed approach, with MoP blocks requiring less than ~1.5% of the adaptive logic modules (ALMs) in a Cyclone V FPGA for interface monitoring and issue mitigation per IP.