A Spike-Event-Based Neuromorphic Processor with Enhanced On-Chip STDP Learning in 28nm CMOS
A Spike-Event-Based Neuromorphic Processor with Enhanced On-Chip STDP Learning in 28nm CMOS
复制标题
基于尖峰事件的神经拟态处理器，在 28nm CMOS 中具有增强型片上 STDP 学习功能
DOI：
10.1109/iscas51556.2021.9401194
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发表时间：
2021
期刊：
影响因子：
--
通讯作者：
Ru Huang
中科院分区：
文献类型：
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作者：
Yi Zhong;Xiaoxin Cui;Yisong Kuang;Kefei Liu;Yuan Wang;Ru Huang
基于事件的脉冲神经网络（SNN）在实现实时、高效、智能的硬件平台方面显示出良好的前景。然而，将在线学习能力引入神经形态系统的可能性仍在探索之中。本文提出了一种28 nm CMOS神经形态处理器，采用计数器和查找表（LUT）的尖峰时间依赖可塑性（STDP）规则实现在线学习。设计工作在高精度的情况下，所提出的处理器集成了多达1024个神经元和256K签署的9位突触。它还确保芯片阵列互连，以适应大型神经网络。此外，通过利用尖峰事件的稀疏特性来最小化活动率，用于训练MNIST数据集的典型功耗进一步降低到3.348mW。
Event-based spiking neural network (SNN) has displayed a promising prospect to realize real-time, efficient and intelligent hardware platforms. Whereas great efforts are still being appealed to explore the possibility of introducing online learning abilities to neuromorphic systems. In this paper, a 28-nm CMOS neuromorphic processor is presented, fulfilling online learning by adopting counter and lookup table (LUT) based spike-timing-dependent plasticity (STDP) rule. Designed to work at high-precision scenarios, the presented processor integrates up to 1024 neurons and 256K signed 9-bit synapses. It also ensures chip array interconnection to fit large neural networks. Moreover, by utilizing the sparse property of spike events to minimize activity rate, the typical power consumption is further reduced to 3.348mW for training MNIST dataset.