An efficient current-based logic cell model for crosstalk delay analysis
An efficient current-based logic cell model for crosstalk delay analysis
复制标题
用于串扰延迟分析的高效的基于电流的逻辑单元模型
DOI：
10.1080/00207217.2012.713015
复制
发表时间：
2009
期刊：
影响因子：
--
通讯作者：
H. Zhou
中科院分区：
文献类型：
--
作者：
D. Das;W. Scott;Shahin Nazarian;H. Zhou
Logic Cell modeling is an important component in the analysis and design of CMOS integrated circuits, mostly due to nonlinear behavior of CMOS cells with respect to the voltage signal at their input and output pins. A current-based model for CMOS logic cells is presented which can be used for effective crosstalk noise and delta delay analysis in CMOS VLSI circuits. Existing current source models are expensive and need a new set of Spice-based characterization which is not compatible with typical EDA tools. In this paper we present Imodel, a simple nonlinear logic cell model that can be derived from the typical cell libraries such as NLDM, with accuracy much higher than NLDM-based cell delay models. In fact, our experiments show an average error of 3% compared to Spice. This level of accuracy comes with a maximum runtime penalty of 19% compared to NLDM-based cell delay models on medium sized industrial designs.
