Throughput-driven IC communication fabric synthesis
Throughput-driven IC communication fabric synthesis
复制标题
吞吐量驱动的 IC 通信结构综合
DOI：
10.1145/774572.774613
复制
发表时间：
2002
期刊：
影响因子：
--
通讯作者：
L. Pileggi
中科院分区：
文献类型：
--
作者：
Tao Lin;L. Pileggi
随着系统集成规模的不断增大，片上通信成为系统性能的最终瓶颈和系统架构的主要决定因素。在本文中，我们提出了一种基于优化总线模型的片上通信结构的吞吐量驱动的综合方法。与传统的延迟驱动的逐线规划方法相比，吞吐量驱动的方法提供了一种可行且准确的系统级解决方案，可以在早期设计规划期间同时解决延迟和拥塞问题。与传统的方法，这是基于相当不准确的RC模型和简单的延迟度量，在我们的方法的通信结构的特点是在现实的部分元件等效电路（PEEC）提取的多层互连和晶体管级瞬态分析，通过SPICE类工具。所表征的模型促进了灵活的互连结构优化引擎，其可以被嵌入到系统规划器中以用于吞吐量驱动的合成。此外，工程权衡考虑中继器面积和互连功耗进一步被认为是这种方法的一部分。
As the scale of system integration continues to grow, the on-chip communication becomes the ultimate bottleneck of system performance and the primary determinant of system architecture. In this paper we propose a throughput-driven synthesis methodology for on-chip communication fabrics based on optimized bus models. Compared with traditional delay-driven, wire-by-wire planning methods, the throughput-driven methodology provides a feasible and accurate system-level solution to address delay and congestion problems simultaneously during early-phase design planning. Unlike the conventional methods which are based on rather inaccurate RC models and simplistic delay metrics, in our methodology the communication fabrics are characterized in terms of realistic Partial Element Equivalent Circuits (PEEC) extracted from the multi-layer interconnects and transistor level transient analysis via SPICE-like tools. The characterized models facilitate a flexible interconnect fabric optimization engine that can be embedded into a system planner for throughput-driven synthesis. Furthermore, engineering trade-offs considering repeater area and interconnect power consumption are further considered as part of this methodology.