A High-Performance and Cost-Effective Hardware Merge Sorter without Feedback Datapath
A High-Performance and Cost-Effective Hardware Merge Sorter without Feedback Datapath
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无反馈数据路径的高性能且经济高效的硬件合并排序器
DOI：
10.1109/fccm.2018.00038
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发表时间：
2018
期刊：
影响因子：
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通讯作者：
Kenji Kise
中科院分区：
文献类型：
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作者：
M. Saitoh;E. Elsayed;Thiem Van Chu;Susumu Mashimo;Kenji Kise
为了开发最快的硬件排序加速器，我们提出了一种高性能、低成本的无反馈数据路径的硬件合并排序器。现有hms的工作频率受到反馈数据路径的严重限制。我们展示了消除反馈数据路径的思想，并提出了采用该思想的具体架构和一些实现优化。评估结果表明，与最先进的HMS相比，我们的HMS以更少的硬件资源实现了1.59倍的吞吐量提升。
We propose a high-performance and cost-effective hardware merge sorter (HMS) without any feedback datapaths in order to develop the fastest hardware sorting accelerator. The operating frequencies of existing HMSs are severely limited by the presence of feedback datapaths. We show the idea of eliminating the feedback datapaths, and propose a concrete architecture adopting the idea and some implementation optimizations. The evaluation results show that our HMS achieves 1.59x throughput improvement with less hardware resources compared to the state-of-the-art HMS.