A resonant signal driver for two-phase, almost-non-overlapping clocks
A resonant signal driver for two-phase, almost-non-overlapping clocks
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用于两相、几乎不重叠时钟的谐振信号驱动器
DOI：
10.1109/iscas.1996.541916
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发表时间：
1996
期刊：
影响因子：
--
通讯作者：
N. Tzartzanis
中科院分区：
文献类型：
--
作者：
W. Athas;L. Svensson;N. Tzartzanis
我们描述了一种驱动电路，用于降低驱动重负载信号（例如 VLSI 芯片的时钟线）时的功耗。该设计在很宽的频率范围内表现出良好的功率效率。我们使用原型移位寄存器芯片测试了驱动器，该芯片的时钟线负载为数百皮法。在 13 MHz 和 5 V 条件下，最坏情况下的总体耗散为 fCV/sup 2/ 的 35%。
We describe a driver circuit for reducing the power dissipated when driving heavily loaded signals such as the clock lines of a VLSI chip. The design exhibits good power efficiency across a wide range of frequencies. We have tested the driver with a prototype shift-register chip which had a clock line load in the hundreds of picofarads. The worst-case overall dissipation was 35% of fCV/sup 2/ at 13 MHz and 5 V.