Readout system with 2-channel 8-bit 1GHz FADC based on RAIN1000Z1 ZYNQ module for crystal detector
Readout system with 2-channel 8-bit 1GHz FADC based on RAIN1000Z1 ZYNQ module for crystal detector
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DOI：
10.1109/rtc.2016.7543096
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发表时间：
2016-06
期刊：
影响因子：
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通讯作者：
T. Xue;G. Gong;Jianmin Li
中科院分区：
文献类型：
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作者：
T. Xue;G. Gong;Jianmin Li
RAIN1000Z1是我们近两年开发的高性能读出模块。它基于Xilinx的ZYNQ架构SOC芯片，ZYNQ是具有双高性能ARM Cortex-A9处理器和大容量可编程逻辑的全新架构FPGA。我们使用基于ZYNQ架构的RAIN1000Z1模块开发了一系列读出系统。对于晶体闪烁体探测器，例如我们在 CJPL（中国金平地下实验室）实验中用于中子本底测量的聚四氟乙烯容器中的 BC-501A 液体闪烁体，我们开发了带有 RAIN1000Z1 模块的两通道 8 位 1GHz FADC 读出系统。利用探测器双端的两个R1250 PMT，将模拟信号发送到FADC，并在FPGA逻辑中对数字结果进行触发和反符合，最终触发数据通过运行嵌入式Linux的ARM处理器通过千兆位以太网发送到计算机。 8位1GSPS模拟数据转换器采用ADI公司的HMCAD1511，高速、低抖动的1GHz时钟由TI公司的LMK04803B产生。借助 ARM 处理器 (PS) 和 FPGA 逻辑 (PL) 之间的高带宽和高性能互连 HP 总线，FPGA 逻辑收集的 FADC 数据被缓冲并传输到 ARM 处理器的 DDR3 SDRAM，运行频率为 1066MHz，具有 CDMA 功能，无需太多 CPU 时间。读出接口的数据吞吐量可通过千兆以太网达到600Mbps以上。本文将详细介绍硬件设计和HDL设计。
RAIN1000Z1 is a high performance readout module we developed last two years. It is based on the ZYNQ architecture SOC chip from Xilinx and ZYNQ is the new architecture of FPGA with dual high performance ARM Cortex-A9 processors and high capacity programmable logic. We developed a series of readout system with the RAIN1000Z1 module based on ZYNQ architecture. For the crystal scintillator detectors, such as BC-501A liquid scintillator in a Teflon vessel we used for neutron background measurement in CJPL (China JinPing under-ground Lab) experiment, we developed a two channels 8-Bit 1GHz FADC readout system with RAIN1000Z1 module. With the two R1250 PMTs in the dual end of detector, the analog signals are send to FADC and the digital results is triggered and anticoincidence in the FPGA logic, the final triggered data is send to computer by gigabits Ethernet with ARM processor running Embedded Linux. HMCAD1511 from ADI is used for 8-Bit 1GSPS analog data converter, and the high speed, low jitter 1GHz clock is generated by LMK04803B from TI. With the benefit of high bandwidth and high performance inter connected HP bus between ARM processor (PS) and FPGA logic (PL), the FADC's data gathered by FPGA logic is buffered and transferred to the ARM processor's DDR3 SDRAM running at 1066MHz with CDMA function without many CPU time. The readout interface's data throughput can reach more than 600Mbps with gigabits Ethernet. In this paper, details of the hardware design and HDL design will be introduced.