Design for Testability for Path Delay Faults in Sequential Circuits
Design for Testability for Path Delay Faults in Sequential Circuits
复制标题
时序电路路径延迟故障的可测试性设计
DOI：
10.1145/157485.164973
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发表时间：
1993
期刊：
影响因子：
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通讯作者：
M. Bushnell
中科院分区：
文献类型：
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作者：
T. Chakraborty;V. Agrawal;M. Bushnell
通过实验研究了几种时序基准电路中路径延迟故障覆盖率低的原因。未发现故障的原因分为三类：(A)组合非激活路径，(B)顺序非激活路径，(C)不可观测的故障效应。正如其他人所讨论的，只有通过修改或重新综合组合逻辑才能使A型故障可被检测到。我们发现，几乎80%的顺序未测试的故障属于B类故障。大多数故障未被激活，因为在顺序电路中不能产生创建转换并通过路径传播该转换所需的两个连续状态。我们研究了部分扫描技术，在该技术中，触发器被扫描以中断循环，并且证明了大幅增加路径延迟故障的覆盖率是可能的。
We experimentally study the reasons for low coverage of path delay faults in several sequential benchmark circuits. Causes for undetected faults are classified into three categories: (A) Combinationally nonactivated paths, (B) Sequentially nonactivated paths, and (C) Unobservable fault effect. The type A faults can only be made detectable by modifying or resynthesizing the combinational logic as has been discussed by others. We find that almost 80% of sequentially untested faults are in category B. Most are not activated because the two successive states necessary to create a transition and to propagate it through the path cannot be produced in the sequential circuit. We study the partial scan technique in which flipflops are scanned to break cycles and show that a substantial increase in the coverage of path delay faults is possible.