Interconnect effort - a unification of repeater insertion and logical effort
Interconnect effort - a unification of repeater insertion and logical effort
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互连工作 - 中继器插入和逻辑工作的统一
DOI：
10.1109/isvlsi.2003.1183353
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发表时间：
2003
期刊：
影响因子：
--
通讯作者：
W. Burleson
中科院分区：
文献类型：
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作者：
Srividya Srinivasaraghavan;W. Burleson
互连在深亚微米设计中的重要性日益增加，然而工业设计实践与均匀中继器插入的经典结果之间存在显著差距。这项工作的问题学术互连电路的两个标准假设：1）中继器的大小和间距的均匀性和2）逻辑和互连之间的边界。本研究探讨了逻辑尺寸和中继器插入的协同设计，以改善延迟，功耗和布局。逻辑努力的技术被用来开发的大小计划的逻辑，包括极性的考虑。非均匀中继器插入用于联合收割机级联调整和分布式线路缓冲。针对0.18/spl mu/技术进行的HSPICE模拟表明，将大小相同的逻辑与均匀中继器相结合比使用最小大小的逻辑电路快约10%，而使用非均匀中继器的增益约为15%。非均匀直放站插入的平均功耗比均匀直放站插入的平均功耗低20%左右。非均匀中继器插入也不太对放置敏感（将设置中的每个中继器的位置移位约40%导致仅约3%的延迟损耗，而对于均匀中继器，延迟损耗约为20%）。
Interconnects are assuming increasing importance in deep submicron design, however there is a significant gap between industrial design practice and classical results of uniform repeater insertion. This work questions two of the standard assumptions of academic interconnect circuits: 1) the uniformity of repeater sizes and spacing and 2) the boundary between logic and interconnects. This research explores the co-design of logic sizing and repeater insertion for improved delay, power and placement. The technique of logical effort is used to develop the sizing scheme for the logic including polarity considerations. Non-uniform repeater insertion is used to combine cascaded sizing and distributed wire buffering. HSPICE simulations carried out for the 0.18/spl mu/ technology show that combining the sized logic with uniform repeaters is faster than using minimum sized logic circuitry by about 10% while with non-uniform repeaters the gain is about 15%. The average power consumption of non-uniform repeater insertion is less than that of uniform insertion by about 20%. Non-uniform repeater insertion is also less placement sensitive (shifting the position of each repeater in the setup by about 40% results in a delay loss of only about 3% while for uniform repeaters the delay loss is about 20%).