A 6.4-Gb/s Near-Ground Single-Ended Transceiver for Dual-Rank DIMM Memory Interface Systems
A 6.4-Gb/s Near-Ground Single-Ended Transceiver for Dual-Rank DIMM Memory Interface Systems
复制标题
用于双列 DIMM 内存接口系统的 6.4Gb/s 近地单端收发器
DOI：
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发表时间：
2013
影响因子：
5.4
通讯作者：
L. Luo
中科院分区：
文献类型：
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作者：
Michael Bucher;R. Kollipara;Bruce Su;L. Gopalakrishnan;K. Prabhu;P. Venkatesan;K. Kaviani;B. Daly;Bill Stonecypher;W. Dettloff;Teva Stone;F. Heaton;Yi Lu;C. Madden;S. Bangalore;J. Eble;N. Nguyen;L. Luo
本文介绍了一种非对称 6.4 Gb/s 内存接口，适用于桌面和服务器应用的各种 DIMM 配置。该链路使用飞越正交转发时钟来实现 DRAM 上的快速启动和功率模式转换以及控制器上的每比特时序调整以实现高速信令。引入单端低摆幅近地信号传输 (NGS) 是为了最大限度地降低信号传输功率。发送器和接收器均衡在控制器上使用，但不在 DRAM 上使用，以节省 DRAM 的复杂性和功耗。提出了架构和电路技术来解决所探索的配置中遇到的复杂信号和时序环境。所实现的链路通过 3.5 英寸 FR4 PCB 走线与双列双列直插内存模块实现 6.4 Gb/s 通信，整个芯片的功率效率优于 9.1 pJ/位。
This paper describes an asymmetric 6.4-Gb/s memory interface for a wide range of DIMM configurations for desktop and server applications. The link uses a fly-by quadrature forwarded clock to enable fast startup and power-mode transitions on the DRAM and per-bit timing adjustment on the controller to enable the high-speed signaling. Single-ended low-swing near-ground signaling (NGS) is introduced in order to minimize signaling power. Transmitter and receiver equalization are used on the controller, but not the DRAM, in order to save DRAM complexity and power. Architectural and circuit techniques are presented to address the complex signaling and timing environment encountered in the explored configurations. The implemented link achieves 6.4-Gb/s communication over a 3.5-in FR4 PCB trace with a dual-rank dual-in line memory module with better than 9.1-pJ/bit power efficiency for the entire chip.