An FPGA implementation of a custom JPEG image decoder SoC module
An FPGA implementation of a custom JPEG image decoder SoC module
复制标题
定制 JPEG 图像解码器 SoC 模块的 FPGA 实现
DOI：
10.1109/ccece.2017.7946826
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发表时间：
2017
期刊：
影响因子：
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通讯作者：
R. Muscedere
中科院分区：
文献类型：
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作者：
G. Kyrtsakas;R. Muscedere
当今的移动的设备的一个重要特征是它们能够在可接受的时间量内捕获和显示高分辨率照片。这些图像存储在使用JPEG编解码器的移动终端上的闪存中，JPEG编解码器几乎有四分之一个世纪的历史，但仍然是行业标准。随着移动的图像传感器和屏幕上的像素数不断增加，软件解决方案将难以在合理的时间内解码JPEG图像数据，因为它们仅依赖于不断增加的CPU能力。在解码大图像时，硬件加速取代CPU的需求越来越明显。本文提出了一种片上系统（SoC）模块，它能够减轻计算密集的JPEG图像解码任务的CPU。该SoC模块在Xilinx Zynq（一种集成了ARM双核667 MHz Cortex A9 CPU和阿蒂克斯-7 FPGA的设备）上开发和测试。在50 MHz下运行的SoC模块能够比板载CPU上运行的软件平均高出4.25倍，同时对原始图像更准确。加速归因于一种新颖的霍夫曼解码器，其在单个周期中操作。
An important feature of today's mobile devices is their ability to capture and display high resolution photos in an acceptable amount of time. These images are stored in flash memory on the mobile device using the JPEG codec which is almost a quarter of a century old but remains the industry standard. With increasing pixel counts on both mobile image sensors and screens, software solutions will struggle in their ability to decode JPEG image data in a reasonable time since they rely solely on increasing CPU power. The need is becoming clearer for hardware acceleration to replace the CPU when decoding large images. This paper presents a System-on-Chip (SoC) module that is able to relieve the CPU of the computationally intense task of decoding a JPEG image. This SoC module was developed and tested on Xilinx Zynq (a device which integrates an ARM dual core 667 MHz Cortex A9 CPU and an Artix—7 FPGA). The SoC module operating at 50 MHz was able to outperform software running on the onboard CPU by an average of 4.25 times while being more accurate to the original image. The speed up is attributed to a novel Huffman decoder which operates in a single cycle.