RIA: Combining Static and Dynamic Techniques for ExploitingLocality

这项研究的最终目标是开发复杂的 并行机的编译器。 记忆延迟是我们的重点 研究，因为它是推动许多设计的瓶颈 并行架构中的决策。 随着系统变得越来越大， 越来越难以让所有内存接近所有内存， 处理器，这可能会增加有效的内存延迟。 电流 减少内存延迟的解决方案可以分为以下两类 动态或静态。 动态解决方案包括多缓存和共享 虚拟内存 这些方法基于以下假设： 程序表现出高度的本地性，因此， 服务高速缓存未命中或页面错误可以分摊在许多时间上 引用该高速缓存行或页。 目前的静态解决方案依赖于 程序员有效地使用内存。 3相关研究 方向提出：一个静态的解决方案的问题 减少了有效的内存延迟， 程序员对机器的了解比目前的解决方案更好， 结合使用静态和动态技术来减少内存 延迟，以及利用局部性的静态和动态方法， 递归定义的动态数据结构。

The ultimate goal of this research is to develop sophisticated compilers for parallel machines. Memory latency is the focus of our research because it is the bottleneck that drives many design decisions in parallel architectures today. As systems become larger, it is increasingly difficult to have all memory close to all processors which can increase effective memory latency. Current solutions for reducing memory latency can be categorized as either dynamic or static. Dynamic solutions include multi-caches and shared virtual memory. These methods are based on the assumption that programs exhibit a high degree of locality and therefore, the cost of servicing a cache miss or a page fault can be amortized over many references that cache line or page. Current static solutions rely on the programmer to use memory efficiently. Three related research directions are proposed: a static solution to the problem of reducing effective memory latency that requires much less detailed knowledge of the machine by the programmer than present solutions, the combination of static and dynamic techniques for reducing memory latency, and static and dynamic methods for exploiting locality in recursively defined dynamic data structures.//