Research Initiation Award: Communication and Fault Tolerance in Parallel Computers

本计画主要探讨大规模平行电脑设计中两个重要且相互关联的问题：处理器间通讯与容错。研究的本质是一个综合的理论和实践方法的并行计算。 高效的处理器间通信是高效并行计算的核心。 除了一些例外，大部分的理论工作都集中在可证明的最优算法上，这些算法往往过于复杂而无法实现。 另一方面，许多实现的路由硬件具有更简单的设计，但缺乏理论上的保证，以他们的性能。 这个项目将试图弥合这一差距，并专注于简单的路由方案，证明是好的（虽然不总是最佳的）。 容错在具有大量易出错组件的并行计算机世界中变得越来越重要。 容错路由方案的研究集中在算法，即使在存在故障的交换机，可以有效地路由数据包。 这两个研究方向代表了非常重要但在很大程度上未知的领域。 第一个问题涉及网络容错的内在限制。 第二个研究方向涉及重新配置在日益重要的一类并行计算机被称为异构并行计算机。

The project focuses on two important inter-related issues in the design of large scale parallel computers: inter-processor communication and fault-tolerance. The nature of the research is one of synthesizing theoretical and practical approaches to parallel computing. Efficient inter-processor communication is at the heart of efficient parallel computing. With some exceptions, much of the theoretical work has focused on provably optimal algorithms that are often too complex to implement. On the other hand, much of the implemented routing hardware have simpler designs but lack theoretical guarantees as to their performance. This project will attempt to bridge this gap and focus on simple routing schemes that are provably good (though not always optimal). Fault tolerance is becoming ever-increasingly important in the world of parallel computers with a large number of fallible components. The study of fault-tolerant routing schemes focuses on algorithms that can route packets efficiently even in the presence of faulty switches. The two research directions represent very important but largely uncharted territory. The first concerns the question of intrinsic limitations on the fault tolerance of networks. The second research direction concerns reconfiguring in increasingly important class of parallel computers known as heterogeneous parallel computers.