Engineering Faculty Internship: A Seamless Environment for Productivity Enhancement; Design Synthesis

9412705 Pandya这个暑期教师实习允许研究人员参与工业设计，发展他们自己的现实设计实例，将这些经验纳入大学教授的超大规模集成电路（VLSI）课程，并开发对学生和工业工程师都有用的视频教程。该项目处理中级任务，并使用两个独立的商业工具从顶层设计、与预先设计/供应商提供/定制的模块的综合、优化和反向注释接口映射到底层或物理设计。这个项目的材料是针对VLSI系统设计的高级本科/研究生课程。

9412705 Pandya This summer faculty internship permits the investigators to be involved in industrial designs, evolve their own realistic design examples, incorporate such experiences in the Very Large Scale Integrated Circuits (VLSI) courses taught at the university and develop video tutorials useful for both the students and industry engineers. This project addresses the intermediate-level tasks and uses two separate commercial tools for mapping from top-level design, synthesis with pre-designed/vendor-supplied/custom-built modules, optimization and back-annotation interfaces to low-level or physical design. This project's material is targeted to senior undergraduate/graduate courses on VLSI System design.