SBIR Phase I: Scalable Distributed Parallel Logic Simulation for Large Deep Submicron VLSI Designs

这个小型企业创新研究第一阶段项目将研究使用先进的UNIX工作站进行大型深亚微米超大规模集成电路设计的并行逻辑模拟的可行性。 集成电路上实现的晶体管数量每2到3年翻一番。这一事实影响了设计方法的所有方面，包括需要数天至数周计算来验证VLSI设计正确性的设计模拟。此外，包含数百万个门的设计不能作为一个单一的系统进行模拟，因为它们要么太大而不适合今天的工作站，要么产生太多的页面错误，使模拟太慢。 本项目将研究一种可扩展的体系结构，用于在UNIX工作站上执行分布式和并行数字逻辑仿真。分布式特性处理了大小问题，消除了页面错误问题。可扩展和并行功能使其能够模拟数百万门设计。 第一阶段的工作将建立架构要求，开发架构，在系统级推导必要的算法，开发一个缩放版本，并分析可以获得的潜在性能。国家的最先进的逻辑模拟和并行处理技术将用于这项工作。将验证该架构是否符合电子设计自动化（EDA）行业标准，以便实现商业化。 所提出的体系结构具有开发和商业化三种产品的潜力：（1）可扩展的分布式并行Verilog（模拟器）;（2）可扩展的分布式并行VHDL模拟器;（3）可扩展的分布式并行协同模拟器。

This Small Business Innovation Research Phase I project will study the feasibility of parallel logic simulation for large deep submicron VLSI designs using advanced UNIX workstations. The number of transistors implemented on an integrated circuit doubles every 2 to 3 years. This fact affects all the aspects of the design methodology, including design simulation that takes several days to weeks of computing to verify the correctness of a VLSI design. Moreover, designs that contain multi-million gates can not be simulated as a single system since they are either too big to fit on today's workstations, or generate too many page faults making the simulation too slow. This project will investigate a scalable architecture for performing distributed and parallel digital logic simulation on UNIX workstations. The distributed feature deals with the size and eliminates the page-fault problem. The scalable and parallel feature makes it possible to simulate multi-million gate designs. The Phase I effort will establish architecture requirements, develop the architecture, derive necessary algorithms at the system level, develop a scaled version and analyze the potential performance that can be obtained. State-of-the-art logic simulation and parallel processing technology will be used for this effort. Verification will be made that the architecture is compliant with the Electronic Design Automation (EDA) industry standard so that commercialization is possible. The proposed architecture has the potential to develop and commercialize three products: (1) Scalable Distributed Parallel Verilog( Simulator; (2) Scalable Distributed Parallel VHDL Simulator; and, (3) Scalable Distributed Parallel Co-Simulator.