Actor-Oriented Synthesis and Optimization of Digital Hardware/Software Systems at System-Level

该项目的目标是可持续地改进嵌入式系统领域中以数据流为主的应用程序在性能以及能源和成本效率方面的异构性多处理器系统。为此，提出了在系统级对嵌入式系统进行综合和优化的新方法。从面向参与者的应用描述出发，研究了自动设计空间探索的方法，以识别解决方案，作为模型精化和最优(部分)硬件和软件解决方案综合的起点。作为第一个重要步骤，在第一个资助期内研究了特定领域的优化和综合方法。特别是，已经表明，对于由静态数据流参与者组成的岛屿，新的集群方法允许准确的分析，并将定时特性、能量消耗和成本降至最低。在第二个资助期，那些提高质量和降低复杂性的系统综合方法将以许多不同的方式进行扩展：在规范方面，将研究适用于更一般模型的新的聚类方法，特别是具有动态参与者行为的应用。在减少单处理器软件实现的调度开销的背景下基本考虑的集群方法将扩展到多处理器目标平台。通过这一点，实现了互连网络上的数据流量的预调度，这有望显著地减少通信和仲裁开销。此外，通过将聚类应用于高级综合，从而实现硬件综合，我们提出了一种新的跨海高级综合方法。与通常只允许有效地合成单个行为者的现有工具相比，这种对整个集群的整体合成保证了大量的能量和成本改进(例如，芯片面积)。最后，在设计空间探索过程中应该无缝地支持集群方法。结果，可以从跨越硬件/软件边界的新颖方法中受益，并且结果，以特定于应用的方式改进了重要的实现属性，例如，性能、能量和成本效率。在该项目中开发的方法可以被认为与现有的系统综合方法是正交的，并作为可持续降低嵌入式系统设计复杂性的新起点。

The goal of this project is to sustainably improve the implementation of dataflow-dominated applications in the domain of embedded systems as heterogeneous multiprocessor system with respect to performance as well as energy and cost efficiency. For this purpose, novel methods for the synthesis and optimization of embedded systems at system-level are developed. Starting from an actor-oriented application description, approaches for automatic design space exploration are studied in order to identify solutions, which serve as starting point for model refinement and synthesis of optimal (partial) hardware and software solutions. As a first important step, domain-specific optimization and synthesis approaches have been studied during the first funding period. In particular, it has been shown that novel clustering methods for islands consisting of static dataflow actors allow for an accurate analysis and the minimization of timing properties, energy con-sumption, and cost. In the second funding period, those quality improving and complexity reducing system synthesis methods will be extended in many different ways: On the specification side, novel clustering methods for more general models, especially applications with dynamic actor behavior, will be studied. The clustering methods, which have been basically considered in the context of scheduling overhead reduction of single-processor software implementations, will be extended towards multi-processor target platforms. By this, a prescheduling of data traffic on the interconnection network is achieved, which is expected to significantly reduce the communication and arbitration overhead. Moreover, by applying clustering during high-level synthesis, and thus hardware synthesis, we propose a novel transactoral high-level synthesis methodology. In contrast to available tools, which often only permit the efficient synthesis of single actors, such a holistic synthesis of a complete cluster promises substantial energy and cost improvements (e.g., chip area). Finally, the clustering methods should be seamlessly supported during design space exploration. As a consequence, it is possible to benefit from the novel methods across hardware/software boundaries and, as a result, important implementation properties, e.g., performance, energy, and cost efficiency, are improved in an application-specific way. The methods, which are developed within this project, can be seen to be orthogonal to existing system synthesis approaches and serve as a new starting point to sustainably reduce the complexity in embedded systems design.