Research in Multithreaded Dataflow and Hybrid Architectures

研究的总体目标是调查的架构功能的成本效益，主流计算的基础上多线程。 在这种情况下，本研究将集中在两个方向;调查多线程的Bullow-von Neumann范式，并适应混合Bullow-von Neumann架构的结果。 该模型非常适合多线程架构，因为它有利于指令级上下文切换和细粒度并行。 对支持多线程的问题有一个清晰的理解，这将使我们能够使它们适应混合的控制流/控制流架构。 混合系统在多处理领域提供了最有趣的机会-它们直接解决未来超标量处理器将面临的问题，如长内存延迟，上下文切换开销，多个活动指令流，快速有效地支持任务同步。 最初，这个项目将调查使用高速缓冲存储器的多线程的并行架构，和编译器技术，以提高这种机器的性能。 这个项目将研究多线程的体系结构支持，包括对线程管理、线程调度、线程间通信和同步的支持。 同时多线程的上下文中的低和混合体系结构，然后将进行调查。 最后，这个项目将探讨最重要的架构功能与传统RISC技术的适用性。

The overall objective of the research is the investigation of architectural features for cost-effective, mainstream computing based on multithreading. In this vein, this research will focus in two directions; investigation of multithreaded dataflow paradigm, and the adaptation of the results to hybrid dataflow-von Neumann architecture. The dataflow model is ideally suited for multithreaded architecture since it facilitates instruction level context switching and fine-grained parallelism. A clear understanding of the issues in supporting multiple threads in dataflow environment will permit us to adapt them to hybrid dataflow/control flow architectures. Hybrid systems present the most interesting opportunities in the area of multiprocessing - they directly address problems that will be faced by future superscalar processors, such as long memory latencies, context switching overheads, multiple active instruction streams, fast and efficient support for task synchronization. Initially, this project will investigate the use of cache memories for multihreaded dataflow architecture, and compiler techniques for improving the performance of such machines. This project will then study architectural support for multithreading including support for thread management, thread scheduling, communication and synchronization among threads. Simultaneous multithreading in the context of dataflow and hybrid architectures will then be investigated. Finally, this project will explore the suitability of the most significant architectural features for use with convectional RISC technology.