CAREER: On Equipping Virtual Path-Based ATM Networks with Fault-Tolerant and Real-Time QoS Capabilities
CAREER: On Equipping Virtual Path-Based ATM Networks with Fault-Tolerant and Real-Time QoS Capabilities
批准号:
9625064
负责人:
Jennifer Hou
金额:
$20.5万
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
1996
资助国家:
美国
项目状态:
已结题
起止时间:
1996-09-01 至 2000-08-31
中文摘要
这项研究的主要目标是建立一个统一的框架,以解决ATM网络的及时性和可靠性要求。提出的研究的中心是ATM网络中的虚路径/虚电路(VP/VC)概念。基于VP/VC的概念,本课题考虑了如何1)通过设计快速恢复机制使ATM网络具有容错能力;2)通过设计VC路由选择方案为ATM网络用户提供实时的服务质量保证。在设计快速恢复机制的背景下,工作将集中于1)在系统初始化时为每个主VP选择备用VP(主VP上的业务将在节点/链路故障时被切换到该备用VP),以及2)动态地重新定位用于在故障时穿过故障节点/链路的第二代备用VP或备用VP的路由。在通过可变数量的VP建立具有实时QOS要求的VC的背景下,工作将集中于1)为每个选定的VC路由(即,VP序列)建立正式的基础,用于测试在该路由上的每个VP上是否有足够的带宽来满足用户指定的端到端延迟要求;以及2)详细阐述在具有足够带宽的所有可能的路由中识别穿越最小数量的VP的VC路由的可能方法。所有建议的组件方案将被一致地合并到ATM流量控制体系结构的VP层中。结合这项研究,PI将把研究和软件实施纳入教学。
英文摘要
The primary objective of the research is to establish a unified framework for addressing timeliness and dependability requirements for ATM networks. Central to the proposed research is the virtual path/virtual circuit (VP/VC) concept in ATM networks. Based on the VP/VC concept, this project considers how to 1) equip ATM networks with fault tolerant capability by designing a fast restoration mechanism; and 2) provide ATM network users with the real-time QoS guarantees by devising a VC route selection scheme. In the context of designing a fast restoration mechanism, work will focus on 1) selecting at system initialization, for each primary VP, a backup VP (to which the traffic on the primary VP will be switched upon node/link failure) and 2) dynamically relocating routes for second-generation backup VPs or backup VPs that traverse the failed node/link upon failure. In the context of establishing VCs with real-time QoS requirements through a variable number of VPs, work will focus on 1) establishing a formal basis for testing, for each selected VC route (i.e., a sequence of Vps) if there is sufficient bandwidth on each VP on the route to meet the user-specified end-to-end delay requirements; and 2) elaborating on possible approaches to identifying a VC route which traverses a minimum number of VPs among all possible routes with sufficient bandwidth. All the component schemes proposed will be coherently incorporated into the VP layer of the ATM traffic control architecture. In conjunction with the research, the PI will incorporate the research and software implementation into teaching.
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