课题基金 / 基金详情

CISE-NSF-CNPq Collaboration Research

CISE-NSF-CNPq Collaboration Research
CISE-NSF-CNPq 合作研究
批准号:
9877171
负责人:
Nader Bagherzadeh
金额:
$15.0万
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
1999
资助国家:
美国
项目状态:
已结题
起止时间:
1999-08-01 至 2001-07-31

项目摘要

项目成果

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中文摘要
翻译
通过加州大学欧文分校(UCI)和巴西里约热内卢联邦大学(UFRJ)的研究人员和学生之间的密切合作,该项目涉及开发一种新的可重构计算架构,称为MorphoSys。这种独特的架构在同一芯片上结合了可重构的单指令多数据(SIMD)协处理器和RISC核心微处理器。此外,为了满足图像/信号处理应用的特殊需求,MorphoSys架构包括一个独特的图像数据缓冲区,用于高效的数据流。M1芯片的行为级模拟表明,该架构对于各种应用(MPEG-2和ATR)非常有前途,其性能远优于标准通用微处理器,接近基于专用asic的解决方案。UCI和UFRJ的研究人员一直在密切合作开发M1芯片的行为模型。UFRJ课题组设计了用于控制M1中SIMD协处理器的RISC内核。该模块被认为是芯片中最复杂的组件之一,需要定制以及可合成的电路。建议UFRJ组处理RISC核心的物理设计,而UCI组完成M1芯片的剩余模块,估计有超过150万个晶体管。除了物理设计,UCI和UFRJ的两个团队之间的其他合作目标包括M1的编程和测试环境的开发,广泛应用的映射和性能评估,以及MorphoSys架构的第二版本的设计。我们认为,此次合作将为UCI和UFRJ在巴西的学生提供一个在竞争激烈、目标明确、多元文化的环境中使用最新技术工作的机会,从而提高他们的教育体验。
英文摘要
This project involves development of a new reconfigurable computing architecture, called MorphoSys, through close collaboration among researchers and students at University of California, Irvine (UCI) and the Federal University of Rio de Janeiro (UFRJ). This unique architecture combines a reconfigurable Single Instruction Multiple Data (SIMD) coprocessor with a RISC core microprocessor on the same chip. Moreover, in order to address the special needs of image/signal processing applications, the MorphoSys architecture includes a unique image data buffer for efficient data streaming. Behavioral level simulation of the M1 chip has shown the architecture to be quite promising for a variety of applications (MPEG-2 and ATR), achieving performance much more superior to the standard general purpose microprocessors and close to specialized ASIC-based solutions.The UCI and UFRJ researchers have been working closely for the development of the behavioral model of M1 chip. The UFRJ research group has designed the RISC core that is used for controlling the SIMD coprocessor in M1. This block is considered one of the most complex components of the chip requiring custom-made as well as synthesizable circuits. It is proposed that UFRJ group handle the physical design of the RISC core, while the UCI group completes the remaining blocks of the M1 chip that is estimated to have more than 1.5 million transistors. Along with physical design, the other objectives for collaboration between the two groups at UCI and UFRJ include development of programming and testing environment for M1, mapping and performance evaluation for a wide range of applications, and design of second version of the MorphoSys architecture. We visualize that this collaboration will enhance the educational experience of students both at UCI and at UFRJ in Brazil, by providing them an opportunity to work in a competitive, target-oriented, multi-cultural environment using the latest technology.
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