CAREER: Architecture Issues in DRAM Devices and Systems

处理器和内存速度之间的差距是当今计算机系统中的一个主要瓶颈。增加DRAM带宽和减少访问时间是解决内存延迟问题的关键。关于DRAM设备和系统的体系结构研究相对匮乏；因此，在该领域有许多代表开放研究的基本问题。本项目研究各种技术在设计DRAM系统中的效果。例如，支持并发访问和确定现代CPU可以在多大程度上利用这种支持；多个通道的影响以及它们是联合在一起以增加带宽还是应该独立运行；以及银行处理的影响及其对DSP和嵌入式应用程序的最佳程度。对于突发模式的DRAM，本项目分析了同时适应并发和快速端到端延迟的最佳突发大小。分析了存储和交织程度、总线宽和总线速在功耗、性能和成本方面的权衡。该教育计划包括开发一门关于存储系统设计和优化的课程。

The gap between the processor and memory speeds is a major bottleneck in today's computer systems. Increasing DRAM bandwidth and reducing access time are keys to solving the memory latency problem. There is a relative dearth of architecture studies on DRAM devices and systems; there are therefore many fundamental questions representing open research in the field. This project investigates into the effects of various techniques in designing a DRAM system. Examples include supporting concurrent accesses and determining the extent to which modern CPUs can exploit such support; the effect of multiple channels and whether they be ganged together to increase bandwidth or should they operate independently; and the effect of banking and its optimal degree for DSP and embedded applications. For burst-mode DRAMs, the optimal burst size to accommodate both concurrency and fast end-to-end latency is analyzed in this project. The tradeoffs between the degrees of banking and interleaving, and between bus width and bus speed in power, performance, and cost are also analyzed. The educational plan involves developing a course on memory-systems design and optimization.