Architectural Support for Scalable High-Speed Routers

可扩展的高速路由器是处理互联网中快速增长的流量所必需的，其聚合数据包转发速率预计将达到每秒太比特。为了跟上未来的传输技术，本文提出了一种具有良好可扩展性和每秒转发数亿个数据包的新型路由器架构。它旨在帮助推进最先进的路由器设计，并使大型网络配置成为可能。该项目包含基础研究和实验系统活动，包括主要目标：(1)开发快速分组分类子系统（PCS），（2)追求用于互连线卡的可扩展交换结构（SSF），(3)评估同步多线程SMT处理器的使用，以取代每个转发引擎中的传统处理器，以及4）调查关键路由器组件的有效容错方案。前三个目标与路由器的可伸缩性和性能有关，而最后一个目标是提高可靠性，随着路由器规模的增长，这一点尤为重要。提出的快速pc包括多个转发引擎和一种新的面向缓存的多级结构（COMS），它将到达线卡的数据包定向到这些转发引擎进行表查找。COMS将查找结果缓存在其组成交换元素上，以便对后续数据包进行快速并发查找。每个转发引擎只保留部分路由/过滤器查找表，而不是完整的查找表（与任何其他路由器设计一样）。SSF基于PI早期的交换结构工作，具有一组适当的环绕连接和用于硬件多播支持的附加逻辑。关于使用SMT处理器处理多个表查找进程（每个进程使用一个线程）的初步研究令人鼓舞，并且将在本项目中进行广泛的评估。在COMS中缓存最佳查找结果将正式建模为图形优化问题，并开发其解决方案。该项目的研究成果可能会对未来的路由器设计产生实质性的积极影响，推动网络技术的发展，促进互联网在未来几年的持续扩展。它们还将丰富计算机通信与网络、网络计算和分布式系统等课程的教学材料。

Scalable high-speed routers are necessary to handle rapidly growing traffic in the Internet at the aggregated packet forwarding rates expected to reach terabits per second. This proposal deals with a novel router architecture with good scalability and capable of forwarding hundreds of millions of packets per second, in order to keep up with future transmission technologies. It aims to help advance the state-of-the-art of router design and to enable large networking configurations. The project contains both basic research and experimental systems activities, including the major objectives of (1) developing a fast packet classification subsystem (PCS), (2)pursuing a scalable switching fabric (SSF) for interconnecting line cards,(3) assessing the use of a simultaneous multithreading SMT) processor to replace the conventional processor(s) in each forwarding engine, and 4) investigating into effective fault-tolerant schemes for key router components. The first three objectives are related to router scalability and performance,whereas the last one is for reliability improvement, which is especially crucial as the router sizes grow. The fast PCS proposed comprises multiple forwarding engines and a novel cache-oriented multistage structure (COMS), which directs packets arriving at line cards to those forwarding engines for table lookups. The COMS caches lookup results at its constituent switching elements to enable fast and concurrent lookups of subsequent packets. Each forwarding engine keeps only partial routing/filter lookup tables, rather than full ones (as in any other router design). The SSF is based on PI's earlier switching fabric work, with an appropriate set of wrap-around connections and additional logics for hardware multicast support. An initial study on the use of an SMT processor to handle multiple table-lookup processes, with one thread for a process, is encouraging, and its extensive assessment will be conducted in this project. Caching lookup outcomes optimally in COMS will be modeled formally as a graph optimization problem, with its solution being developed. Research results from this project are likely to have material, positive impacts on future router design, advancing networking technologies to facilitate the continuous expansion of the Internet for years to come. They will also enrich the lecturing materials of such courses as computer communications and networks, network computing, and distributed systems.