CAREER:The Evaluation and Design of a Scalable, High Performance and Energy Efficient Microprocessor Architecture

推测性执行在计算机体系结构研究中被广泛使用，以追求更高级别的指令级并行性。然而，最近的研究表明，这种技术会显著影响处理器流水线的可伸缩性。本研究将从性能、可扩展性、能量效率、面积和复杂性方面对一些推测技术进行研究，最终得出一种新的、可扩展的架构，以提供未来技术规模的高性能。这种架构将最小化处理器关键时序路径上的逻辑量，依赖于较小的推测结构来减少处理器的周期时间。在关键路径之外，各种更大的推测结构为关键路径提供了退位存储。本研究中要考察的一些技术包括分支预测、值和地址预测、数据预取、提前寄存器释放和延迟寄存器分配以及多集群功能单元。这些技术中的许多都需要大型且往往复杂的预测器，这可能会影响处理器的周期时间和功率密度。这项研究调查了一些技术，以减少这些结构的访问时间和大小，同时仍然提供精度，以避免昂贵的投机性恢复过程。

Speculative execution has been widely used in computer architectureresearch in the pursuit of higher levels of instruction levelparallelism. However, recent studies have shown that this techniquecan significantly impact the scalability of the processor pipeline.This research will investigate a number of speculative techniqueswith respect to performance, scalability, energy efficiency, areacosts, and complexity; eventually leading to a novel, scalablearchitecture to provide high performance at future technology sizes.Such an architecture will minimize the amount of logic on thecritical timing path of the processor, relying on small speculativestructures to reduce the cycle time of the processor. Off thecritical path, a variety of larger speculative structures provide abacking store to the critical path.Some of the techniques to be examined in this research includebranch prediction, value and address prediction, data prefetching,early register release and late register allocation, and multipleclustered functional units. Many of these techniques require largeand often complex predictors that can impact the cycle time and powerdensity of a processor. This research investigates some techniquesto reduce the access time and size of these structures, while stillproviding the accuracy to avoid costly speculative recoveryprocedures.