ITR Collaborative Research: Programmable Graph Architecture for High Level Transformations of Multimedia Applications

用于多媒体应用高级转换的可编程图架构摘要在本研究中，我们将研究转换算法、架构和可编程图架构的设计，以将多媒体操作的高级表示直接映射到硬件中。我们期望这种空间映射将大大增加处理器芯片的计算密度，特别是对于那些广泛使用矩阵运算的计算。这些可编程图架构的计算将依赖于矩阵群和Cayley图之间的变换，而不是传统微处理器使用的传统算术和逻辑运算。特别是，我们计划：(i)为多媒体应用程序的计算效率高的可编程图形架构建立一个指令集；（ii）提供有效的算法，将这些指令转换为Cayley图中的图路由问题；（iii）研究与凯莱图设计参数相关的优化问题。我们希望这项研究能够带来下一代多媒体机器架构的原型，这些架构可能与当今传统的细粒度微架构有很大的不同。由于多媒体在日常应用中的作用越来越大，设计和开发高效的多媒体处理器体系结构变得非常重要。

Programmable Graph Architectures For High Level Transformations ofMultimedia ApplicationsAbstractIn this research we will investigate transformational algorithms, architecture, and design of programmable graph architectures, to map high-level representations of multimedia operations directly into hardware. We expect that this spatial mapping will substantially increase the computational density of processor chips, especially for those computations that make extensive use of matrix operations. The computations on these programmable graph architectures will rely on transforms between matrix groups and Cayley graphs rather than traditional arithmetic and logic operations used by conventional microprocessors. In particular, we plan to: (i) establish an instruction set for programmable graph architectures that is computationally efficient for multimedia applications; (ii) provide efficient algorithms to transform these instructions to graph routing problems in Cayley graphs; and (iii) examine the optimization issues pertaining to the design parameters of Cayley graphs.We expect this investigation to lead to prototypes of next generation multimedia machine architectures that are likely to be significantly different from the conventional fine-grained microarchitectures of today. The design and development of efficient multimedia processor architectures is important due to the increasing role of multimedia in everyday applications.