Asynchronous Circuits and Systems for Nanoelectronics

PI: Martin, Alain J.机构：加州理工学院标题：纳米电子学的异步电路和系统预计，CMOS，当今半导体集成电路的选择技术，将很快遇到基本的物理限制，主要是由于用于图案电路的光刻工艺。在所有可能的后继技术中，基于碳纳米管和纳米线的非光刻分子电子技术是最有前途的技术之一。由于固有的制造困难，这些技术中的电路将在物理参数上表现出很大的变化，以及很大比例的故障和缺陷。在纳米时代，考虑参数可变性、缺陷和容错将是任何成功电路设计方法的内在组成部分。由于电参数的任何变化都会对电路的时序行为产生影响，因此能够以一种使电路的正确行为与时序无关的方式设计电路是一个很大的优势，因为它将大大增加电路对参数变化的鲁棒性。这种设计风格被称为“异步”。本研究的目的是发展一种基于异步逻辑的分子电子集成电路的设计方法，包括容错和容错电路技术。使用异步逻辑的另一个原因是，在典型的数字系统（如微处理器）中，这种逻辑不需要时钟来实现操作顺序。在芯片上分配时钟信号需要具有良好平衡定时特性的长导线，这在分子电子学中是不可能做到的。该研究将开发设计方法来处理硬缺陷（如断线）和软（或瞬态）错误（如由α粒子撞击电路并将位从0变为1引起的）。处理硬错误将需要冗余，以便能够使用“备件”和可重构性，以便在运行中重新设计电路以规避错误。对于电路中所有这些不可预测的变化，异步提供的时间独立性将是一个很大的优势。由于制造过程的非光刻性质，分子电子学限制了芯片的几何形状。从本质上讲，导线既可以南北向运行，也可以东西向运行，所有有源器件（晶体管）都建在南北导线和东西向导线的交叉点上。这种受限的几何结构需要像fpga这样的大型规则结构，而不是具有任意几何结构的随机逻辑。在这种受限的几何形状下进行设计（不同方向的导线之间存在非常高的电阻接触问题）是该项目的另一个挑战。该项目将提出并测试基于碳纳米管和纳米线的分子电子器件的完整异步逻辑家族，以及处理故障和缺陷容错不同方面的设计方法。希望能设计并制造出一种重要的芯片，例如小型微控制器。

Prop ID: CCF-0541461 PI: Martin, Alain J. Institution: California Institute of Technology Title: Asynchronous Circuits and Systems for Nanoelectronics It is expected that CMOS, today's technology of choice for semiconductor-based integrated circuits, will soon run into fundamental physical limits mainly due to the lithographic process used to pattern the circuits. Among all possible successors, non-lithographic molecular-electronic technology based on carbon nanotubes and nanowires is one of the most promising. Because of inherent fabrication difficulties, circuits in those technologies will exhibit large variations in physical parameters as well as large percentage of faults and defects. Taking parameter variability and defect- and fault-tolerance into account will be an inherent part of any successful circuit design methodology in the nanoscale era. Because any variation in an electrical parameter has an effect on the timing behavior of the circuit, being able to design a circuit in a manner such that the correct behavior of the circuit is independent of the timing is a great advantage since it would greatly increase the robustness of the circuit to parameter variations. Such a design style is called ``asynchronous''. The purpose of this research is to develop a design method for molecular-electronic integrated circuits based on asynchronous logic, including error- and defect-tolerance circuit techniques. Another reason for using asynchronous logic is that such logic does not need a clock to implement the sequencing of actions in a typical digital system like a microprocessor. Distributing a clock signal across a chip requires long wires with well-balanced timing properties, which is impossible to do in molecular electronic.The research will develop design methods to deal with both hard defects like broken wires, and soft (or transient) errors as caused for instance by an alpha particle hitting the circuit and changing a bit from zero to one. Dealing with hard errors will require redundancy to be able to use ``spares'' and reconfigurability to redesign a circuit on the fly to circumvent an error. For all those unpredictable changes in the circuit, independence of timing offered by asynchrony will be a great advantage.Because of the non-lithographic nature of the fabrication process, molecular electronics restricts the geometry of the chips. Essentially, a wire can run either north-south or east-west, and all active devices (transistors) are built at the intersection between a north-south wire and an east-west one.This restricted geometry calls for large regular structures like FPGAs, rather than random logic with arbitrary geometry. Designing within this restricted geometry (with the additional issue of very highly resistive contacts between wires of different direction) is another challenge of this project.The project will propose and test a complete asynchronous logic family for molecular electronic devices based on carbone nanotubes and nanowires and a design method to deal with different aspects of fault- and defect-tolerance. It is hoped that a significant chip, for instance a small microcontroller, will be designed and fabricated.