Cyber System:Research: Security Aware Design for Test Methods

可测试性设计(DFT)技术通过改进从主输入对内部节点的控制或通过改进对主输出处的内部节点上的值的观察，或通过这两者来改进对硬件设备的内部状态的访问。另一方面，从安全的角度来看，硬件设备应该将内部状态的可控性和可观测性降到最低，从而最大限度地减少/消除对芯片上敏感信息的访问。需要保护的敏感信息可能包括存储在密码设备上的密钥、包含在设计中的有价值的知识产权和在通用处理器上运行的安全软件。智力优势：将调查传统DFT技术在各种设备(包括密码硬件、运行安全软件的嵌入式处理器和包含有价值知识产权的硬件设备)中引入的安全漏洞。并不是所有的DFT技术都可能引入安全漏洞。即使是给定的DFT技术也可能不会在所有芯片和所有嵌入式处理器中引入安全漏洞。例如，在具有超过数万个触发器的大型芯片和处理器中，测试数据通常在芯片上进行压缩。这本身就使攻击者的任务相当困难，甚至是不可能的。然而，在用于低端智能卡的嵌入式处理器和密码加速器中，由于触发器的数量有限，测试数据没有被压缩。我们将通过考虑这些因素来系统地表征漏洞。还将研究在不损害安全性的情况下提高可测试性的DFT机制。PIS还将通过了解流行的扫描DFT及其变体(如带有芯片压缩和解压缩电路的扫描)引入的旁路，研究可测试性和安全性之间的相互作用和权衡，并开发具有安全意识的DFT技术，如安全扫描和加密扫描。最后，该提案将通过发起基于DFT的攻击来验证安全感知DFT技术，这些攻击很容易受到攻击，并通过评估结果的可测性来验证。广泛的影响：这项研究将在不损害普通民众财务和医疗安全的情况下，为智能卡和植入式生物医学电子设备带来好处。这项研究将证明，安全性是任何设计的重要设计指标，而不仅仅是安全硬件。这项研究将对理工学院和伊利诺伊大学的研究生和本科生的教育起到突出的作用。PIS将在面向研究生项目的课程中引入安全意识测试。优秀的本科生将参与与这个项目相关的项目，作为计算机工程序列本科高级设计项目的一部分。在伊利诺伊大学，PI将改革一系列课程，专注于安全嵌入式系统设计。

Design for Test (DFT) techniques improve access to the internal state of hardware devices either by improving control of internal nodes from the primary inputs or by improving observation of values on internal nodes at the primary outputs or both. On the other hand, from a security perspective, hardware devices should minimize the controllability and observability of the internal state to a minimum and thereby minimize/eliminate access to sensitive on-chip information. The sensitive information that needs to be protected may include secret keys stored on cryptographic devices, valuable Intellectual Property incorporated into designs and security software running on general purpose processors.Intellectual merit: The security vulnerabilities introduced by traditional DFT techniques in a variety of devices including cryptographic hardware, embedded processors running security software and hardware devices that contain valuable intellectual property will be investigated. Not all DFT techniques may introduce security vulnerabilities. Even a given DFT technique may not introduce security vulnerabilities in all chips and in all embedded processors. For example, in large chips and processors with over tens of thousands of flip flops, test data is typically compressed on chip. This in itself makes the task of an attacker quite difficult nay impossible. However, in embedded processors and crypto accelerators used in low end smart cards, test data is not compressed owing to the limited number of flip flops. We will systematically characterize the vulnerabilities by accounting for these factors. The DFT mechanisms that improve testability without compromising security will also be investigated. The PIs will also study the interaction and trade-offs between Testability and Security by understanding the side channels introduced by popular Scan DFT and its variants such as scan with on-chip compression and decompression circuitry and develop security-aware DFT techniques such as secure-scan and encrypted-scan. Finally, the proposal will validate the security-aware DFT techniques by launching DFT-based attacks that they were vulnerable to and by evaluating the resulting testability.Broader impacts: This research will bring the benefits of smartcard and implantable biomedical electronic devices without compromising their financial and medical security to the general population. The research will demonstrate that security is an important design metric of any design and not just security hardware. This research will play a prominent role in the education of graduate and undergraduate students at Polytechnic and at University of Illinois. The PIs will introduce security aware test in a graduate project oriented courses. Outstanding undergraduates will participate in projects related to this project as part of an undergraduate Senior Design Project for Computer Engineering sequence. At University of Illinois, the PI will reform a sequence of courses to focus on secure embedded system design.