Runtime reconfigurable analog circuits and adaptive filter synthesis for compensation of unreliable hardware constraints

CMOS工艺的持续缩小是由数字电路的需求主导的，因为存储器和高性能cpu是VLSI的驱动力。虽然晶体管的缩放使速度和功率效率得以提高，但它也为深亚微米技术引入了各种新的工艺变化和器件退化来源。PP 1500的第一阶段表明，数字电路中各种硬件施加的影响以瞬态位翻转故障的形式传播到逻辑级。因此，它们可以在更高的数字硬件级别上处理，甚至可以在软件中处理，这是许多正在进行的项目所涵盖的。然而，对模拟电路的深亚微米效应的研究表明，这些在模拟电路设计中引入了一类新的故障：除了在制造过程中相当高的模拟参数不匹配外，现在还需要考虑退化效应，这些效应会在系统运行期间导致持续退化，直至功能的永久破坏。克服这些问题的传统模拟设计方法是过度设计，这在许多情况下抵消了技术扩展的好处。嵌入式系统通常需要利用模数转换器（adc）的传感器接口，其中又包括敏感的模拟部件。这些电路的过度设计可能会在功耗和面积消耗方面超过数字部分，这对于嵌入式系统的外围部件是不希望的。因此，申请人在PP 1500的第一阶段研究了模拟电路弹性的另一种方法，该方法引入了可重构模拟部分的数字监测和控制。由于一种结构上可重构的模拟滤波器的新方法，与专用asic相比，只有很少的性能权衡，因此可以忽略可靠性的过度设计。相反，模拟部分的缺陷被考虑在内，这些缺陷的补偿被转移到数字域，其中-由于缩小-更多的计算能力是可用的。虽然PP 1500的第一阶段用于进一步改进可重构模拟滤波器，但现在可以在第二阶段将其包含在一个独立的弹性ADC中，用于混合信号soc。研究重点是数字辅助电路，它将实现模拟部分的性能测量以及优化算法，以便通过运行时重新配置ADC前端滤波器来在线监测和优化模拟性能。辅助电路的通信接口将允许与嵌入式系统的所有层次进行交互。两者都可以广播模拟参数的运行时变化，也可以接收性能约束，以便调整到整体系统要求。

The ongoing downscaling of CMOS processes is dominated by the demands of digital circuits, since memories and high-performance CPUs are the driving forces of VLSI. While transistor scaling has enabled improvements in speed and power-efficiency, it has also introduced various new sources of process variation and device degradation to deep submicron technologies. The first phase of the PP 1500 showed that various hardware-imposed effects in digital circuits are propagated to the logic-level as transient bit-flip faults. Thus, they can be handled either at higher digital hardware levels or even in software, which is covered by many ongoing projects. However, investigation of deep submicron effects on analog circuits showed that these introduce a new class of faults into analog circuit design: In addition to considerably higher mismatch of analog parameters during manufacturing, there are now also degradation effects to be considered, which cause continuous degradation during runtime of the system up to permanent destruction of the functionality. The traditional analog design approach to overcome these problems was overdesign, which in many cases countervails the benefits of technology scaling. Embedded systems commonly require sensor interfaces that utilize analog-to-digital converters (ADCs), which in turn include sensitive analog parts. Overdesign of these circuits for yield and reliability may exceed the digital part in terms of power- and area-consumption, which is undesirable for peripheral parts of embedded systems. Thus, the applicant investigates another approach to resilience of analog circuits during the first phase of PP 1500, which introduces digital monitoring and control of a reconfigurable analog part. Due to a novel approach to structurally reconfigurable analog filters with only little performance tradeoff against dedicated ASICs, it is possible to omit overdesign for reliability. Instead, imperfections of the analog part are taken into account, and compensation of these imperfections is shifted to the digital domain, where – due to downscaling – ever more computation power is available. While the first phase of PP 1500 was used to further improve the reconfigurable analog filter, it is now possible in the second phase, to include it into a self-contained resilient ADC for use in mixed-signal SOCs. The research focus is the digital assistance circuitry, which will be implementing performance measures of the analog part as well as optimization algorithms to allow online monitoring and optimization of the analog performance through runtime reconfiguration of the ADC frontend filter. A communication interface to the assistance circuitry will enable interaction with all hierarchy-levels of the embedded system. Both, runtime changes of analog parameters can be broadcasted, as well as performance constraints can be received, in order to adjust to overall system requirements.