Dependability Aspects in Configurable Embedded Operating Systems -- DanceOS

未来嵌入式系统的硬件设计将以更低的可靠性为代价，展现出更高的并行性和能效。这给系统软件带来了新的挑战，特别是操作系统（OS），它必须使用和提供软件措施来补偿不可靠的硬件。DanceOS项目通过一种新的基于资源高效的软件容错技术的组合解决了操作系统设计的这些挑战，这些技术可以通过面向方面的编程灵活地应用于操作系统和应用程序，由基于工具的（半）自动分析应用程序和操作系统代码驱动，导致后者在硬件容错方面严格以问题为导向进行调整。第三个资助期的主要目标是：为了扩大我们对硬件/软件栈中操作系统上下层的研究范围，（2）改进和优化我们的方法和工具，以更好地了解它们的基本限制。在操作系统层之上，我们将特别关注分布式环境中多线程服务的强化。下面的操作系统，我们认为架构与非易失性存储器作为一个热门话题，必须解决。这些系统提供了新的基于软件的容错措施和非常快速（潜在的细粒度）的错误恢复机制的机会。另一方面，非易失性存储器承担的风险，把软错误变成永久性failure.In不正确的处理，除了优化资源效率，我们面向方面的容错措施，结合全程序分析，我们计划探索替代开发方法的基础上代码生成。其结果将是一个高度可靠的（AN编码）OSEK类RTOS，这将-通过与以前的作品相比-导致对使用通用方面语言进行基于软件的容错的基本限制的见解。我们的可靠性分析基础设施将进行优化，以更快地产生结果，而对结果质量的影响非常小。这将允许开发人员将我们的评估工具集成到开发周期中。 贯穿大多数工作包的一个反复出现的主题是我们的故障模型的扩展。虽然在主存储器和CPU寄存器中的一位翻转在以前的项目阶段占主导地位，我们现在的目标是将最近的研究结果更现实的伊萨和子ISA故障模型。

Future hardware designs for embedded systems will exhibit more parallelism and energy efficiency at the price of being less reliable. This bears new challenges for system software, especially the operating system (OS), which has to use and provide software measures to compensate for unreliable hardware. The DanceOS project addresses these challenges for OS design by a novel combination of resource-efficient software-based fault-tolerance techniques, which can flexibly be applied to the OS and the application by means of aspect-oriented programming, driven by a tool-based (semi-)automatic analysis of the application and OS code, resulting in a strictly problem-oriented tailoring of the latter with respect to hardware-fault tolerance.The main goals for the third funding period are (1) to broaden the scope of our research towards the layers above and below the OS in the hardware/software stack and (2) to refine and optimize our methods and tools to gain a better understanding of their fundamental limits.On top of the OS layer, a special focus will be on hardening multi-threaded services in distributed environments. Below the OS, we regard architectures with nonvolatile memories as a hot topic that must be addressed. These systems provide opportunities for novel software-based fault-tolerance measures and very fast (potentially fine-grained) error-recovery mechanisms. On the other hand, nonvolatile memories bear the risk of turning soft errors into permanent failure if not handled correctly.In addition to optimizing the resource efficiency of our aspect-oriented fault-tolerance measures by incorporating whole-program analysis, we plan to explorean alternative development approach based on code generation. The result will be a highly-dependable (AN-encoded) OSEK-like RTOS, which will -- by comparison to previous works -- lead to insights about fundamental limits of using general-purpose aspect languages for software-based fault tolerance. Our dependability analysis infrastructure will be optimized to yield results much faster with only very small compromises regarding result quality. This shall allow developers to integrate our assessment tools into the development cycle. A recurring topic throughout most work packages is the extension of our fault models. While single-bit flips in main memory and CPU registers were dominant in previous project phases, we now aim at incorporating recent research results on more realistic ISA- und sub-ISA fault models.