SGER: Dynamic Partitioned Global Address Spaces for Future Large Scale Systems

随着电子信息的持续爆炸性增长，商业企业和高性能计算系统都被构建为互连的模块计算/存储模块或刀片的大型集合。这些系统构成了下一代数据中心和超级计算机，它们成功广泛部署的一个主要障碍是不断增长的资本成本以及电力和冷却成本。造成这些成本的主要因素是内存子系统，它可能超过处理核心的成本，在高端配置中消耗高达25%-40%的能源。目前，数据中心的体系结构限制了数据中心的物理内存可以被系统中的不同程序共享。因此，系统的设计必须适应最坏情况下的峰值内存需求，因此在资本成本和电力方面都过于昂贵。这项拟议的研究探索了一种新的解决方案，通过使内存能够以动态、需求驱动的方式在刀片之间共享，从而降低与内存系统相关的成本。其核心思想是内存子系统与网络子系统的紧密结合。其结果是显著提高了内存效率，并随之而来的是数据中心的总内存需求下降，而性能几乎没有损失。通过利用芯片集成方面的最新进展，这种方法变得可行，其中存储控制器和高性能通信接口集成在同一芯片上。因此，通过跟踪实际内存需求而不是静态配置最坏情况下的内存需求，可以比以前更有效地管理成本和电力。为了保持其在计算领域的领导地位，美国工业既需要像这里建议的那样的技术进步，也需要利用这些进步的新公司，以及拥有快速技术和产品开发所需技能集的新员工。拟议的工作提供了合适的技术元素，以提供吸引学生参与计算机科学和工程主题的方法，阻止美国CS和CmpE入学人数的持续下降，创造新的就业机会，并利用美国学生群体的创造力和创业性质。通过佐治亚理工学院现有的NSF I/UCRC与IBM、惠普和英特尔等科技公司建立的现有关系将提供影响系统社区的途径。

With the continued explosive growth in electronic information, bothbusiness enterprises and high performance computing systems are beingstructured as large ensembles of interconnected modularcomputing/storage modules or blades. These systems form the nextgeneration data centers and supercomputers and a major impediment totheir successful wide-spread deployment is the growing capital cost aswell as power and cooling costs. A dominant contributor to these costsis the memory subsystem that can exceed the costs of the processingcore and consume as much as 25%-40% of the energy in high endconfigurations. Currently, the architecture of data centers limits howphysical memory in data centers can be shared by different programs inthe system. Consequently, systems must be designed to accommodate theworst case peak memory demand and is therefore unduly expensive bothin terms of capital cost as well as power. The proposed research explores a novel solution for the reduction of memory system related costs by enabling memory to be shared across blades in a dynamic, demand-driven, fashion. The key idea is the tight integration of memory subsystem with the network subsystem. The result is a significant increase is memory efficiency and an attendant drop in the total memory requirements of a data center with little to no performance penalty. This approach is made feasible by exploiting recent advances in chip integration where the memory controllers and high performance communication interfaces are integrated on the same die. Thus cost and power can be more effectively managed than previously feasible by tracking actual memory demand rather than statically provisioning for worst case memory demand.To maintain its leadership in computing, U.S. industry requires bothtechnical advances such as those proposed here, new companies thatleverage these advances, and new employees with the skill sets neededfor rapid technology and product development. The proposed work offerssuitable technical elements to offer ways to engage students inComputer Science and Engineering topics, to arrest the ongoing declinein the U.S. enrollment in CS and CmpE, to create new employmentopportunities and to leverage the creativity and entrepreneurialnature of the U.S. student population. Existing relationships withtechnology companies such as IBM, HP, and Intel through an existingNSF I/UCRCat Georgia Tech will provide pathways to influence the systemcommunity.