SBIR Phase I: Self-Compensating Ultra-Wideband Direct Digital-to-RF D/A Converter

这个小型企业创新研究第一阶段项目试图克服目前阻碍实现急需的低成本高性能数模转换器(DAC)的基本限制，这些DAC可以适应当前和未来通信系统、软件定义无线电(SDR)和广泛的其他应用的宽带。这项研究的重点是开发电路、信号处理和控制算法，这些算法将有效地解决在互补金属氧化物半导体(CMOS)实现的新型DAC拓扑中遇到的损害，该拓扑旨在适应超宽带。虽然可以为数字处理器和存储器量身定做CMOS制造工艺，但对于高性能、宽动态范围的模拟电路的设计来说，这是一个最具挑战性的环境。正在开发的解决方案基本上为DAC提供了自我修复？使其能够克服不可避免的损害，如设备不匹配、非线性和时序不对齐。初步结果表明提出的架构和方法的有效性，预计第一阶段研究将产生可制造的设计。来自学术界的研究人员和博士生参与这项研究，使他们能够接触到半导体行业非常感兴趣的最具挑战性的研究课题。该项目更广泛的影响/商业潜力在于允许将超高性能的数据转换能力集成到低成本的芯片上系统(SoC)解决方案中，这些解决方案广泛用于从通信和多媒体到仪器仪表的各种类型的商业应用。特别是，正在开发的技术将允许在真正的特别提款权中整合和低成本实现这一最关键的功能。拟议的创新旨在通过使用新颖的内置校准和补偿电路和算法，针对不可避免的损害的影响进行自给自足的补偿，例如制造工艺变化、失配、非线性和时序失调，将允许集成DAC提供超高性能(例如，在10 GHz以上的速率下的16位分辨率)，而不需要在制造时进行昂贵的测试、生产成品率损失、激光微调或高性能模拟集成电路的传统设计和制造的任何其他后果。将要开发的方法对芯片制造有更广泛的影响，因为这些损害也代表了其他功能的限制因素。作为一项使能技术，拟议的创新可能会极大地扩大现有数据转换器市场的规模，目前市场规模为30亿美元，并允许各种新的消费类应用程序，这些应用程序需要较宽的操作带宽，但成本受到限制。

This Small Business Innovation Research Phase I project attempts to overcome fundamental limitations that are currently inhibiting the realization of much needed low-cost high-performance digital-to-analog converters (DACs), which can accommodate the wide bandwidths of current and future communication systems, software-defined-radios (SDR), and a wide range of other applications. The focus of this research is the development of circuitry and signal processing and control algorithms that would effectively address impairments experienced in a complementary-metal-oxide-semiconductor (CMOS) implementation of a novel DAC topology designed to accommodate ultra-wide bandwidths. While the CMOS fabrication process may be tailored for digital processors and memory, it is a most challenging environment for the design of high-performance, wide dynamic range analog circuitry. The solutions being developed essentially provide the DAC with ?self-healing? capabilities that allow it to overcome inevitable impairments such as device mismatches, non-linearities, and timing misalignments. Preliminary results indicate the validity of the proposed architectures and approaches and it is anticipated that a fabrication-ready design will result from the Phase 1 research.The involvement of researchers and PhD candidates from academia in this research allows them exposure into most challenging research topics that are of great interest to the semiconductor industry. The broader impact/commercial potential of this project is in allowing ultra-high-performance data-conversion capabilities to be integrated into low-cost CMOS system-on-chip (SoC) solutions that are widely used in commercial applications of various types ranging from communications and multimedia to instrumentation. In particular, the technology being developed will allow for the integration and low-cost realization of this most critical function in a true SDR. The proposed innovation, targeting the self-sufficient-compensation for the effects of inevitable impairments, such as fabrication-process variations, mismatches, non-linearities, and timing misalignments, through the employment of novel built-in calibration and compensation circuitry and algorithms, will allow integrated DACs to deliver ultra-high performance (e.g., 16-bit resolution at rates above 10GHz) without requiring costly testing at fabrication, production-yield losses, laser trimming, or any other consequence of traditional design and manufacturing of high-performance analog integrated circuits. The approach to be developed has a broader impact on chip manufacturing, as these impairments represent limiting factors in other functions as well. As an enabling technology, the proposed innovation can potentially greatly increase the size of the existing market for data converters, currently at $3B, and allow for various new consumer applications where wide bandwidths of operation are needed and cost is a constraint.