EAGER: Integrating Chip Reliability in Designing Energy-Saving Scheduling Algorithms

能源消耗的大幅增加给我们的社会带来了许多严重的工程问题和经济问题。在过去的十年里，人们提出了许多节能调度算法来管理电力消耗。然而，节能算法对芯片寿命可靠性的影响，这是影响整个系统可持续性的重要因素，尚未被计算机科学理论家仔细研究。本EAGER提案的目标是探索将芯片可靠性纳入现代计算设备节能调度算法设计的理论基础。PI提出了一个新的模型，该模型通过强制附加的芯片寿命可靠性约束来增强现有的能量感知调度程序，这些约束被建模为处理器频率变化的函数。为了解决这一问题，研究了新的调度算法设计和分析技术。项目结果可能潜在地转变为一系列相关的调度问题。除了研究提出的理论问题外，PI还利用FreeBSD操作系统对所开发算法的性能进行了实证测量。本研究表明，通过操作系统内核开发，可以证明理论发现的实际意义。

The substantial increase of energy consumption has brought up many serious engineering problems and economic concerns to our society. Many energy-saving scheduling algorithms have been proposed in the past decade to manage power consumption. However, energy-saving algorithms' impact on chip lifetime reliability, an important factor affecting overall system sustainability, has not been carefully examined by computer science theorists.The goal of this EAGER proposal is to explore the theoretical groundwork of incorporating chip reliability in designing energy efficient scheduling algorithms for modern computing facilities. The PI proposes a new model that augments the existing energy-aware schedulers by enforcing additional chip lifetime reliability constraints which are modeled as functions of processor frequency changes. Novel scheduling algorithm design and analysis techniques are investigated to solve this problem.The project outcome may potentially be transformative to a spectrum of related scheduling problems. In addition to studying the proposed theoretical problems, the PI empirically measures the performance of the developed algorithms by utilizing the FreeBSD operating system. This research suggests that through operating system kernel development, the practical implications of theoretical findings can be demonstrated.