SBIR Phase I: Security Evaluation Platform for Automating Inclusion of Hardware Security in Integrated Circuit Design

这个小企业创新研究（SBIR）第一阶段项目的更广泛的影响/商业潜力是确保集成电路（IC）知识产权（IP）免受全球化IC供应链中不受信任的各方的侵害。集成电路代工厂的外包带来了集成电路逆向工程、生产过剩、盗窃甚至盗版的风险。实现硬件IP安全的一种很有前途的方法是通过用可编程元素替换设计组件的子集来逻辑地锁定设计的功能。这些元素的正确内容构成了在安全设施和/或在制造后通过安全协议解锁/激活设计的关键。将该技术商业化的一个技术挑战是，在设计阶段通常需要很长时间来评估锁定设计的安全性，以对抗最先进的攻击算法。该项目将通过开发一种人工智能（AI）辅助设计安全分析工具来解决这一技术挑战，该工具可以即时为锁定设计提供准确的攻击运行时间估计，从而大大缩短设计时间。这项小型企业创新研究（SBIR）第一阶段项目将大大缩短评估模糊（锁定）集成电路（IC）设计的攻击弹性所需的时间。在最先进的计算机服务器上运行最先进的布尔可满足解算器（SAT攻击）来消除锁定设计的模糊性可能需要几天到几个月的时间。如此长的安全性分析时间对于在设计过程中部署是禁止的，因为在设计过程中需要进行迭代设计优化以进行功率、性能、面积和安全性（PPAS）权衡。该项目旨在通过引入一种新颖的方法来解决这一挑战，该方法将使用基于机器学习的模型将安全评估时间降至接近于零。基于图和几何深度学习技术的最新进展，提出了一种创新的端到端安全评估框架，该框架直接无损地将原始设计作为图结构输入，然后自动学习影响逻辑锁定安全性的判别特征。为了支持所提议的数据驱动方法的足够数据，将开发一个逻辑锁定宏数据库，其中包含所需的PPAS、攻击和防御信息。该奖项反映了美国国家科学基金会的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。

The broader impact/commercial potential of this Small Business Innovation Research (SBIR) Phase I project is to secure Integrated Circuit (IC) Intellectual Property (IP) against untrusted parties in the globalized IC supply chain. Outsourcing of IC foundries creates risks of IC reverse engineering, overproduction, theft, and even piracy. A promising method of achieving hardware IP security is by logically locking the functionality of a design by replacing a subset of the design components with programmable elements. The correct content of these elements forms the key for unlocking/activation of the design in a secure facility and/or via a secure protocol after manufacturing. A technical challenge in commercializing this technology is the long time period typically needed to assess the security of a locked design against state-of-the-art attack algorithms at the design phase. This project will address this technical challenge by developing an Artificial Intelligence (AI)-assisted design security analyzer tool to instantaneously provide an accurate attack runtime estimation on a locked design, significantly reducing the design time.This Small Business Innovation Research (SBIR) Phase I project will significantly shorten the time required to assess attack resiliency of an obfuscated (locked) Integrated Circuit (IC) design. Running the state-of-the-art Boolean Satisfiability solvers (SAT attack) on a state-of-the-art computer server to de-obfuscate a locked design can take time - ranging from days to months. Such a long security analysis time is prohibitive for deployment in the design process where iterative design optimizations are needed for making power, performance, area, and security (PPAS) trade-offs. This project aims to address this challenge by introducing a novel approach that will bring the security assessment time down to near zero using a machine-learning based model. Based on recent advancements in graph and geometric deep learning techniques, an innovative end-to-end security assessment framework is proposed that directly and losslessly ingests the original design as a graph-structured input, and then automatically learns the discriminative features that influence logic locking security. To support sufficient data for the proposed data-driven method, a logic locking macro-database will be developed that encompasses the required PPAS, attack and defense information.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.