SCAD: Synchronous Control Asynchronous Dataflow (SCAD) Architectures

响应式嵌入式实时系统目前通常采用基于模型的设计流程进行开发。特别是，同步模型变得流行起来，其中使用时间驱动的时钟来触发系统的反应步骤。在每个反应步骤中，系统读取其输入并通过执行该宏步骤反应中安排的微步骤动作来计算其输出。典型的设计阶段，如模拟、形式化验证和其他系统分析，如最坏情况反应时间的估计，通过同步模型的确定性和形式化语义来简化。然而，通常的同步模型的软件合成仍然生成一个顺序程序，其中实际并发的微步骤是按照因果正确的顺序安排的。因此，执行这些程序的处理器通常会找到大量的指令级并行（ILP）来提高它们的性能。然而，当前的处理器体系结构（如超标量和VLIW处理器）可以利用的ILP数量相对较低，其中一个特别的原因是寄存器的使用。由于这个原因，“暴露的数据路径架构”（EDPA）已经被开发出来，它允许编译器生成的程序除了控制内部指令调度之外，还控制功能单元的分配和数据传输，而不使用传统的寄存器。在这个项目中，我们开发了一种新的和创新的暴露数据路径架构，称为SCAD（同步控制，异步数据流），它将用于有效地执行具有高度ILP的顺序程序，就像从基于模型的设计流中获得的程序一样。SCAD架构由许多可能特定于应用程序的功能单元（FUs）组成，这些功能单元的输入和输出是（FIFO）缓冲的。SCAD程序由一系列移动指令组成，这些移动指令指示输出缓冲区将计算结果发送到其他功能单元的输入缓冲区。移动指令在生产者和消费者FU中同步注册，以确保每个FU的操作数的正确顺序。然而，FUs的执行将按照数据流顺序进行，因此将自然地利用所包含的ILP。原则上，SCAD体系结构是先前对同步程序的硬件和软件综合研究的结果：它改进了先前的硬件和顺序软件综合方法，甚至可以有效地利用特定于应用程序的FUs。在研究项目中，我们打算在fpga上开发和评估具有不同互连网络的SCAD机器的变体，将开发周期精确的模拟器，以及应该生成近乎最佳代码的高效编译器。此外，我们还计划考虑像分支预测和乱序执行这样的优化，以及作为运行时重构手段的fu的临时耦合。

Reactive embedded real-time systems are nowadays often developed by model-based design flows. In particular, synchronous models became popular, where a time-driven clock is used to trigger the reaction steps of the system. In every reaction step, the system reads its inputs and computes its outputs by executing the micro step actions scheduled in this macro step reaction. Typical design phases like simulation, formal verification, and other system analyses like the estimation of the worst case reaction time are simplified by the deterministic and formal semantics of synchronous models.However, the usual software synthesis of a synchronous model still generates a sequential program where the actually concurrent micro steps are scheduled in a causally correct sequential order. Processors executing these programs will therefore typically find a large amount of instruction-level parallelism (ILP) to increase their performance. However, the amount of ILP that can be exploited by current processor architectures like superscalar and VLIW processors is relatively low, and one particular reason for this is the use of registers. For this reason, `exposed datapath architectures' (EDPA) have been developed which allow the compilers to generate programs that control besides the internal instruction scheduling also the allocation of function units and the data transports without making use of traditional registers.In this project, we develop a new and innovative exposed datapath architecture called SCAD (synchronous control, asynchronous dataflow) that will be used to efficiently execute sequential programs with a high degree of ILP as the ones obtained from model-based design flows. A SCAD architecture consists of a number of possibly application-specific function units (FUs) whose inputs and outputs are (FIFO) buffered. SCAD programs consist of a sequence of move instructions that instruct the output buffers to send the computed results to input buffers of other function units. The move instructions are synchronously registered in the producer and consumer FUs to ensure the correct ordering of operands of each FU. However, the execution of the FUs will proceed in dataflow order and will therefore naturally exploit the contained ILP.In principle, the SCAD architecture is the result of previous research on hardware and software synthesis of synchronous programs: It improves previous approaches to hardware and sequential software synthesis and can even make effective use of application-specific FUs.In the research project, we intend to develop and to evaluate variants of the SCAD machine with different interconnection networks on FPGAs, will develop cycle-accurate simulators, and efficient compilers that should generate nearly optimal code. We moreover plan to consider optimizations like branch prediction and out-of-order execution as well as temporary coupling of FUs as a means for runtime reconfiguration.