Design and Architecture for Racetrack based Hybrid Memory Systems

随着对高性能和低能耗的追求，对存储容量的需求不断增加，使得存储系统的设计变得极其困难。传统的DRAM内存已经达到其基本和物理限制，可能会阻止其容量增长。最近提出的基于自旋轨道电子学的赛道存储器(RTM)是一种新型的存储器存储技术，它在纳米级的磁线上访问和存储二进制数据，允许过高的密度以及克服技术扩展限制的能力。尽管在关键技术上取得了进步，RTM的访问延迟和能量消耗仍然受到轮班操作次数的严重影响。这些操作是将比特移动到跑道中正确位置所必需的。为了能够采用RTM，该方案将RTM与DRAM和自旋传递扭矩(STT)存储器在存储器层次结构中的不同层次相结合，不仅提供了巨大的机会，而且在处理大数据量时也面临着艰巨的挑战。这些系统需要适应应用程序的不同存储器访问模式，同时它们需要避免构成它们的单个存储器的固有限制。这就要求存储系统设计发生根本性的转变，需要重新审视硬件和操作系统层面的数据管理策略，为混合存储系统的高效数据管理奠定基础。我们将通过实现硬件和操作系统的联合优化来实现这一目标，以便应用程序可以利用设想的混合存储系统的内在潜力，尽管异构性带来了额外的复杂性。具体地说，我们将致力于相对较新的RTM的设计及其适配，RTM控制器的设计，数据分类和分析，层次适配，以及全系统数据管理。我们将遵循协同设计方法，以此作为弥合硬件和操作系统层之间差距的一种方式，这种差距因混合存储系统的高中断潜力而大大扩大。在硬件方面，我们将深入研究RTM的体系结构，使其能够与其他存储器高效集成。通过利用硬件性能监视器和智能控制器，我们将全面描述应用程序数据和内存行为的不同属性。这将引导硬件和操作系统(OS)采取适当的数据映射、数据重新映射、RTM适配和层次结构适配决策。我们设想HW-OS协作机制能够持续适应应用程序数据行为和系统负载的变化。因此，该项目将有助于缓解硬件和操作系统层之间的差距，实现相对较新的RTM与成熟的存储技术的有效集成。

The increasing memory capacity requirements along with the quest for high performance and low energy have made the memory system design extremely difficult. The conventional DRAM memory has reached its fundamental and physical limitation that likely prevents it from growing in capacity. The recently proposed spin-orbitronics based RaceTrack Memory (RTM) is a novel memory-storage technology that accesses and stores binary data on nanoscale magnetic wires allowing exorbitant density as well as the ability to overcome the technology scaling limitations. Despite key technological advancements, the access latency and energy consumption of RTM is highly influenced by the number of shift operations. These operations are required to move bits to the right positions in the racetracks. To enable adoption of RTM, this proposal envisions a hybrid memory system by combining RTM with DRAM and Spin Transfer Torque (STT) memories at different levels in the memory hierarchy.The hybrid memory system not only offers huge opportunities but also presents daunting challenges to handle large set of data. These systems need to adapt to the application’s diverse memory access patterns, and at the same time they need to avoid the inherent limitations of individual memories constituting them. This requires a radical shift in the memory system design and a need to revisit data management strategies at hardware and operating system level.The overall goal of this proposal is to lay the foundation for highly efficient data management on hybrid memory system. We will achieve this goal by enabling hardware and operating system joint optimizations so that applications can exploit the inherent potential of the envisioned hybrid memory system despite the extra complexity brought in by heterogeneity. Concretely, we will work on design of relatively newer RTM and its adaptation, on RTM controller design, on data classification and analysis, on hierarchy adaptation, and on system-wide data management. We will follow a co-design methodology as a way to bridge the gap between hardware and operating system layers that is greatly enlarged by the high disruption potential of hybrid memory system. On the hardware side, we will deeply investigate the architecture of the RTM to enable its efficient integration with other memories. By leveraging hardware performance monitors and intelligent controllers, we will fully describe different properties of application data and memory behavior. This will guide the hardware and the operating system (OS) to take appropriate data mapping, data remapping, RTM adaptation, and hierarchy adaptation decisions. We envisage HW-OS collaborative mechanisms to continuously adapt to the change in application data behavior and system load. This project will thus contribute to mitigate the gap between the hardware and operating system layers, enabling efficient integration of relative newer RTM with well-established memory technologies.