An ultra-low-power, modular PSSS-FEC-ARQ combined processor for 100 Gbps wirelesscommunication in the THz-band

虽然最近已经演示了100Gbps的通信，但对于移动设备来说，它仍然消耗太多的硬件资源和能源。因此，需要低复杂度的算法，这些算法可以用于5G和更高的方法。一方面，用于数据处理的各种算法必须是轻量级的，以便以可接受的功耗实现收发机。另一方面，实施必须强大，以缓解在极其苛刻的条件下运行的模拟前端的限制。该项目提出了100Gbps无线通信的模块化体系结构的研究，主要关注功率和能效。将基带处理与前向纠错和自动重发请求相结合，应该会使我们能够更有效地使用能量。此外，模块化基带处理的研究应该允许按照比面向峰值速率的处理更接近的数据速率来跟踪用户需求。这再次对动态功耗产生了很大影响。我们不打算单独构建GT；100 Gbps系统的处理单元，相反，我们建议研究高速移动收发信机的跨层优化和模块化架构。主要目标是尽可能降低基带和错误处理实体(ARQ、FEC)组合的功耗，但低于0.5W@100 Gbps(导致0.5PW/b)。除了该项目直接可见的结果外，这项研究还将产生通信链中信号处理组件的最佳组合的新想法。此外，它将通过使用不同的模块化、多核处理和算法链概念来对大规模超低功耗系统进行新的洞察。

Although 100 Gbps communication has been demonstrated recently, it still consumes too much hardware resources and energy for mobile devices. Thus, there is a need for low complexity algorithms that can be employed for 5G and beyond approaches. On one hand, the various algorithms used for the processing of data have to be lightweight, in order to lead to transceivers realizable with acceptable power consumption. On the other hand, the implementation has to be powerful to mitigate limitations of the analog frontend that operates in extremely demanding conditions. This project proposes the investigation of a modular architecture for 100 Gbps wireless communication with the main focus on power and energy efficiency. Combining the baseband processing with forward error correction and automatic repeat request should allow us to use energy much more efficiently. Moreover, the investigation of modular baseband processing should allow following user demands according data rates much closer than peak-rate oriented processing. This again has high impact on dynamic power consumption. We do not propose to build the individual processing elements of the >100 Gbps system, instead, we propose a research on the demanding cross-layer optimizations and modular architectures for high-speed mobile transceivers. The main target is reducing power consumption as much as possible but below 0.5 W @ 100 Gbps (which results in 0.5 pW/b) for the combined baseband and error handling entities (ARQ, FEC). Beyond the immediate visible results of the project this research will generate new ideas of optimal combination of signal processing components in communication chains. Moreover, it will lead to new insight into massive ultra-low power systems by using different concepts of modularity, multi-core processing and algorithmic chaining.