SMAUG: System-Level Modeling and Optimized Use of Disruptive Memory Technologies

除了处理单元，主存是计算机系统中最重要的资源，没有它，数据处理实际上是不可能的。几十年来，各种类型的随机存取存储器(RAM)一直被用作主存储器。RAM技术正在不断发展，因此获得了更大的容量、更低的访问延迟和更高的数据速率，但主存储器的基本性能保持不变。它传统上是同构的和字节可寻址的。存储器内容是易失性的，即当设备关闭时它们会丢失。此外，它是被动的，即它不能独立处理数据。这些典型的特性现在牢牢地植根于软件开发人员的期望，并相应地体现在他们的产品中。我们现在看到了一波内存技术的创新浪潮，这些创新打破了这些假设。从这个意义上说，它们对整个软件行业和计算机科学都是“颠覆性的”。这方面的例子包括NVRAM(非易失性和非常特殊的性能特征)和第一批允许“内存中处理”(PIM)或“近内存计算”(NMC)(主内存变为活动的)的产品。此外，还有一些技术，如高带宽内存(HBM)和极快的网络，允许“内存解聚”或跨计算机边界的直接内存访问(RDMA)。总而言之，这些创新承诺系统具有更高的处理能力、更低的能源消耗、更高的可靠性和更低的成本。然而，未来的应用程序和系统软件如何以优化的方式使用集成了其中几种技术的复杂平台仍在很大程度上是不清楚的。本项目旨在解决这一问题。第一阶段是关于为新的硬件组件、整个系统的拓扑和软件的行为创建正式模型的方法。模型应该支持灵活的用例，例如运行时或编译时的查询，因此需要可配置的详细级别。它们应该涵盖不同的非功能属性，并具有模块化结构。方法和工具应该支持模型生命周期的所有阶段，即模型的生成、使用和发展。通过对优先程序的中央硬件平台的示例性建模，证明了该方法的实用性。同时，这些模型也可用于其他项目。所考虑的模型是开发优化资源管理策略的重要前提。在它们的帮助下，控制流和数据将以避免瓶颈和未充分利用的方式放置在复杂的系统中。这将在最初只有选择性地进行调查，并在第二阶段进行更深入的调查。

Besides the processing units, main memory is the most important resource in a computer system without which data processing would be de facto impossible. Various types of random access memory (RAM) have been used as main memory for several decades. RAM technology is under continuous development and, thus, got larger capacities, lower access latencies and higher data rates, but the basic properties of the main memory remained unchanged. It is traditionally homogeneous and byte-addressable. Memory contents are volatile, i.e. they are lost when the device is switched off. In addition, it is passive, i.e. it cannot process data independently. These typical properties are now firmly anchored in the expectations of software developers and manifest themselves in their products accordingly. We are now seeing a wave of innovations in memory technologies that defeat these assumptions. In this sense they are “disruptive” for the entire software industry and computer science. Examples of this are NVRAM (non-volatile and very special performance characteristics) and the first products that allow “Processing-in-Memory” (PIM) or “Near Memory Computing” (NMC) (main memory becomes active). In addition, there are technologies such as high-bandwidth memory (HBM) and extremely fast networks that allow “memory disaggregation” or direct memory access across computer boundaries (RDMA). Taken together, these innovations promise systems with higher processing power, lower energy consumption, more reliability and cost reductions. However, it is still largely unclear how complex platforms that integrate several of these technologies can be used in an optimized manner by future application and system software.This project is intended to remedy this. The first phase is about a methodology for creating formal models for the new hardware components, the topology of the overall system and the behavior of the software. The models should support flexible use cases, e.g. queries at runtime or compilation time, and therefore need a configurable level of detail. They should cover different non-functional properties and have a modular structure. Methods and tools should support all phases of the model life cycle, i.e. model generation, use and evolution. The practical suitability of the methodology is demonstrated by the exemplary modeling of the central hardware platform of the priority program. At the same time, the models can be used by other projects.The considered models are a crucial prerequisite for the development of optimized resource management strategies. With their help, control flows and data are to be placed in complex systems in such a way that bottlenecks and underutilization are avoided. This will initially be investigated only selectively and in the second phase in more depth.