Study on automatic parallelizing compiler for multiprocessor systems and architectural supports

在本研究项目中，我们开发了用于多粒度并行处理的数据许可方案，考虑了处理器间数据传输和任务处理的最大重叠以隐藏数据传输开销的多处理器调度算法，以及针对编译器后端的精确机器代码调度方案，以在不降低计算精度的情况下消除并行化机器代码中的所有同步指令。在一个多处理器结构模拟器和一台真实的超级计算机上，使用所提出的对齐数据分解和部分静态分配技术在多处理器结构模拟器上对数据本地化方案进行的性能评估表明，该方案可以将粗粒度并行、循环并行和细粒度并行的多粒度并行处理的平均执行时间分层缩短20%。此外，还证实了隐藏数据传输开销的重叠调度算法在具有4个处理器的富士通VPP500上平均减少了15%的执行时间。近细粒度并行处理方案的开发和评估为高级并行机器代码调度提供了理想的体系结构支持。上述编译方案和使用体系结构模拟器和超级计算机的评估明确了下一代多处理器超级计算机和未来的单芯片多处理器所需的体系结构支持。这些研究成果以15篇期刊或国际会议论文、1篇带综述的研讨会论文、5份技术报告和12篇国内年会短论文的形式发表。

In this research project, we developed data licalization schemes for multigrain parallel processing, multiprocessor scheduling algorithms considering maximum overlap of inter-processor data transfer and task processing to hide data transfer overhead, and precise machine code scheduling schemes for a "compiler back-end" to eliminate all synchronization instructions from parallelized machine code without deteriorating calculation accuracy. Also, we showed effectiveness of the developed schemes on a multiprocessor architecture simulator and a real supercomputer.Performance evaluation on a multiprocessor architecture simulator for the data localization schemes using the proposed aligned data decomposition and partial static assignment techniques showed us that the scheme can shorten average execution time of multigrain parallel processing using coarse grain parallelism, loop parallelism, and fine grain parallelism hierarchically by 20%.Also, it has been confirmed that the overlapping scheduling algorithms to hide data transfer overhead reduce execution time on Fujitsu VPP500 with 4 processors by 15% in average.futhermore, the development and evaluation of near fine grain parallel processing schemes made clear desirable architectural supports for advanced parallel machine code scheduling.The above compilation schemes and evalution using architecture simulator and the supercomputer made us clear necessary architectural supports for next generation multiprocessor supercomputers and a future single chip multiprocessor.These research accomplishment were published as 15 journal or international conference papers, 1 symposium paper with reviews, 5 technical reports and 12 short papers for domestic annual conventions.