Development of New Digital Signal Processing Circuit for Neural and Fuzzy Systems

在数字计算机运算领域，各种VLSI技术以非常高的速度实时处理海量二进制数据，已经越来越多地出于需要而变得更加高效。我们用冗余表示的高基正数实现了新的并行算术和逻辑运算电路，由于其处理速度快，可以有效地消除二进制数具有很大位数长度的运算进位过程中的链传输延迟。为了避免传统模拟神经网络和模糊硬件系统中模拟计算带来的误差，我们试图实现高速、高精度的数字信号处理电路。1998年，我们提出了一种新的最小冗余表示的高基正数(PD)数的高速加法和减法算法，该算法易于转换为非冗余的bin…更多的元数，实现了一种基于电流型的新型五值四基PD数加减法电路。在此基础上，实现了逻辑积、逻辑和、有界和、有界差、有界积的模糊基本逻辑运算电路，以及表示隶属函数模糊等级的两个冗余表示的五值四基正数之间的最大/最小判别。1999年，为了与其他二进制处理系统一起构建复杂系统，我们在第四章提出了新的二进制编码冗余PD数加减法和乘法，每个数字值可以表示为一组复数个非冗余比特值。在逻辑组合开关电路的基础上，构造了一种新型的基于电压型CMOS的加减器，该电路由NOT电路和NAND电路组成。在此基础上，利用超前进位加法运算的变换算法，实现了一种将冗余的4进制PD数转换为纯二进制数的解码器，并利用通用电路仿真软件SPICE对该加法器进行了测试。我们采用了基于0.5μm MOS工艺的增强型PMOS和NMOS的SPICE模型参数。根据测量结果，得到了加法的最大传播延迟时间约为3[ns]。较少

In the field of the digital computer arithmetic, various VLSI technologies for realtime processing of large massive binary data at a very high speed have increasingly come into much efficient meaning out of necessity. We have realized new parallel-processing arithmetic and logical operation circuits using redundantly-represented high-radix positive digit numbers, which can be effective to eliminate the chain transferred delay in the carry process of operation with binary numbers having very large digit-lengths because of its fast processing. By utilizing these basic computation technique for avoiding errors arising from the analog calculation in the conventional analog neural an fuzzy hardware systems, we tried to realize high-speed and high-precision digital signal processing circuits.In 1998, we proposed a new high-speed addition and subtraction algorithm for minimum redundantly-represented high-radix positive digit (PD) numbers which are easy to be transformed into non-redundant bin … More ary numbers, and we realized a new current-mode CMOS-based 5-valued 4-radix PD number addition and subtraction circuit. Furthermore, we realized the fuzzy basic logical operation circuits for logical products, logical sum, bounded sum, bounded difference and bounded product, and max/min discrimination between two redundantly-represented 5-valued 4-radix positive digit numbers which express the fuzzy grades of membership functions.In 1999, in the fourth chapter, in order to construct the complex system with other binary processing systems, we proposed new binary-coded redundant PD number addition, subtraction method and multiplication methods where each digit value can be expressed a set of plural non-redundant bit values. I construct a new voltage-mode CMOS-based adder and subtracter based on logical combinational switch circuit, which is composed of NOT circuits and NAND circuits. Moreover, I realized a new decoder for converting redundant 4-radix PD numbers into pure binary number by using transforming algorithm which is worked as a carry look ahead addition processing.We tested the new adder by using general circuit simulation software, SPICE. We have used the SPICE model parameters of the enhancement type PMOS and NMOS based on the 0.5 μm MOSIS CMOS technology. By the measured results, the maximum propagation delay time of addition are obtained about 3 [ns]. Less