RESERCH ON STRUCTURE METHOD OF VERY HIGH-SPEED MULTIDIMENSIONAL DIGITAL FILTER USING MULTIRATE SIGNAL PROCESSING

1. 本研究提出了一种基于降维分解的可分分母二维状态空间数字滤波器的高性能VLSI架构。为了获得高速实现，我们采用了基于块算法的高度并行架构。为了提高速度，通过使用分布式算法来保持较小的开销，该算法的处理时间仅取决于字长。此外，我们可以通过利用我们之前提出的使用最优功能电路的方法而不是使用ROM的传统分布式算法来大幅降低功耗。通过VLSI评估，我们证明了该架构对于超高清图像是非常高效的。首先，我们提出并分析了不使用乘法器（即不使用乘法器）的分布式算法（DA-ADF） LMS自适应滤波器。本文提出的DA-ADF是一种高性能自适应滤波器，具有速度快、输出延迟小、收敛速度快、硬件规模小、高阶滤波器功耗低等特点。其次，为了进一步提高速度，我们提出了基于分布式算法（BDA）和多内存块结构BDA （MBDA）的块LMS算法。为了实现流水线处理，我们对这些算法应用了一种新的更新方法。我们称这个方法为“优先级更新”。此外，我们提出了一种高效的MBDA-ADF VLSI架构，并评估了采样率和输出延迟。因此，我们的MBDA-ADF可以实现非常高的采样率和小的输出延迟。

1. This research proposed a high-performance VLSI architecture for separable denominator 2-D state space digital filters based on reduced-dimensional decomposition. To obtainhigh-speed implementation, we aplied the highly parallel architecture based on the block algorithm. For the purpose of higher speed, small overhead is kept by using the distributed arithmetic of which processing time depends only on word length. Further, we can substantially decrease power dissipation by taking advantage of not the conventional distributed arithmetic using ROM's, but the method using the optimum function circuits which we have previously proposed. As a result of VLSI evaluation, we showed that this proposed architecture was very efficient for super high definition image.2. Firstly, we proposed and analyzed the LMS adaptive filter using distributed arithmetic (DA-ADF), which used no multipliers (that is multiplier-less). Our proposed DA-ADF is a high-performance adaptive filter which has performances of high speed and small output latency, good convergence speed, small-scale hardware and lower power dissipation for higher order, simultaneously.Secondly, for the purpose of further higher speed, we proposed block LMS algorithm using distributed arithmetic (BDA) and multi-memory block structured BDA (MBDA). To enable the pipelined processing, we applied an new update method to these algorithms. We called the method "priority update". Moreover, we proposed an efficient VLSI architecture of MBDA-ADF, and evaluated the sampling rate and output latency. As a result, our MBDA-ADF can achieve very high sampling rate and smal output latency.