DSP Code Optimization Techniques with Consideration in both Computational Resources and Memory Access

基于一种具有自动修改功能的间接寻址数字信号处理器(以下简称DSP)，提出了一种新的代码优化技术，其中内存分配阶段与计算排序阶段紧密耦合，通常情况下，DSP的软件开发成本很高，因此迫切需要高级语言编译器等强大的编程工具。生成的程序代码的高性能通常是通过有效使用算术单元和寄存器来实现的。然而，在大多数DSP中，存储器寻址模式被简化，高效的存储器访问成为实现高代码性能的另一个关键。在本研究项目中，假设了一种具有自动修改的间接寻址的DSP，其编译器的结构是根据派生的算术寄存器分配和存储器分配在子指令级中间代码中重新安排计算顺序。编译器首先统计给定程序的数据流图(以下称为DFG)中每个变量的使用情况，并选择要溢出的程序变量。对于派生的DFG，通过代码生成和内存分配来评估开销代码的数量。对于有内存访问的可交换算术运算，计算所有可选计算顺序的开销代码数量，最后取开销代码最少的代码作为结果，并将所提出的代码优化技术应用于具有相似内存寻址的mPD77230的现有编译器。对于几个示例，由编译器生成的代码包括与存储器访问相关联的开销代码，这比由传统编译器导出的代码少，因此显示了所提出的代码优化技术的有效性。

An indirect addressing digital signal processors (hereafter DSP) with auto-modification is assumed, a new code optimization technique is proposed, where memory allocation phase is intensively coupled with a computational ordering phase.In general, software development for DSP is highly cost consuming, so that powerful programming tools such as high-level language compiler is strongly desired. High performance in generated program codes is usually achieved by effective use of arithmetic units and registers. In most of DSPs, however, memory addressing modes are simplified and efficient memory access becomes another key to achieve high code performance.In this research project, a DSP with indirect addressing with auto-modification is assumed, and its compiler has such structure that computational order is rearranged in intermediate code of sub-instruction level according to the derived arithmetic register assignment and memory allocation. The compiler first counts usage of each variable in the data flow graph (hereafter DFG) of a given program, and selects program variables to be spilled. For the derived DFG, the number of overhead codes is evaluated by code generation followed by memory allocation. Then for the commutative arithmetic operations with memory access, the number of overhead codes is evaluated for all the alternative computational orders, and finally, the code with least overhead code is taken as the result.The proposed code optimization technique is applied to the existing compiler for mPD77230, which has similar memory addressing. Codes generated by the compiler for several examples includes less overhead codes associated with memory access than those derived by conventional compilers, and hence shows the effectiveness of the proposed code optimization technique.